Albrecht P. Stroele

According to our database, Albrecht P. Stroele authored at least 30 papers between 1990 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Test Scheduling for Minimal Energy Consumption under Power Constraints.

Tobias Schüle, Albrecht P. Stroele

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Scheduling tests for low power built-in self-test.

Tobias Schüle, Albrecht P. Stroele

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes.

Albrecht P. Stroele, Steffen Tarnick

J. Electron. Test., 2000

Synthesis for Arithmetic Built-In Self-Tes.

Albrecht P. Stroele

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

A Versatile BIST Technique Combining Test Registers and Accumulators.

Frank Mayer, Albrecht P. Stroele

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Synthesizing data paths with arithmetic self-test.

Albrecht P. Stroele

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Signature Analysis for Test Responses of Sequential Circuits.

Albrecht P. Stroele

VLSI Design, 1999

Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.

Albrecht P. Stroele, Steffen Tarnick

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.

Albrecht P. Stroele, Frank Mayer

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults.

Gerald Spiegel, Albrecht P. Stroele

VLSI Design, 1998

Hardware-optimal test register insertion.

Albrecht P. Stroele, Hans-Joachim Wunderlich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions.

Albrecht P. Stroele

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Embedded self-testing checkers for low-cost arithmetic codes.

Steffen Tarnick, Albrecht P. Stroele

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit.

Frank Mayer, Albrecht P. Stroele

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Entwurf selbsttestbarer Schaltungen.

Albrecht P. Ströle

Teubner-Texte zur Informatik 27, Teubner, ISBN: 978-3-8154-2314-1, 1998

1997

BIST Pattern Generators Using Addition and Subtraction Operations.

Albrecht P. Stroele

J. Electron. Test., 1997

Methods to reduce test application time for accumulator-based self-test.

Albrecht P. Stroele, Frank Mayer

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996

Test response compaction using arithmetic functions.

Albrecht P. Stroele

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Arithmetic Pattern Generators for Built-In Self-Test.

Albrecht P. Stroele

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Signature analysis and aliasing for sequential circuits.

Albrecht P. Stroele

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Self-Test Approach Using Accumulators as Test Pattern Generators.

Albrecht P. Stroele

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Test register insertion with minimum hardware cost.

Albrecht P. Stroele, Hans-Joachim Wunderlich

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A unified approach to the extraction of realistic multiple bridging and break faults.

Gerald Spiegel, Albrecht P. Stroele

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Configuring Flip-Flops to BIST Registers.

Albrecht P. Stroele, Hans-Joachim Wunderlich

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Signature Analysis for Sequential Circuits with Reset.

Albrecht P. Stroele

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Partitioning and hierarchical description of self-testable designs.

Albrecht P. Stroele

Proceedings of the VLSI 93, 1993

1992

Testablaufplanung und Testauswertung für selbsttestbare Schaltungen.

Albrecht P. Ströle

PhD thesis, 1992

Self-Test Scheduling with Bounded Test Execution.

Albrecht P. Stroele

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Signature Analysis and Test Scheduling for Self-Testable Circuits.

Albrecht P. Stroele, Hans-Joachim Wunderlich

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990

Error masking in self-testable circuits.

Albrecht P. Stroele, Hans-Joachim Wunderlich

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990