Alberto Ros
Orcid: 0000-0001-5757-1064Affiliations:
- University of Murcia, Computer Engineering Department, Spain
According to our database1,
Alberto Ros
authored at least 108 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Computers, February, 2024
Microprocess. Microsystems, 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
J. Parallel Distributed Comput., March, 2023
J. Parallel Distributed Comput., January, 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
J. Supercomput., 2022
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the IEEE International Symposium on Workload Characterization, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
J. Parallel Distributed Comput., 2021
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
IEEE Trans. Parallel Distributed Syst., 2020
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution.
IEEE Trans. Computers, 2020
J. Parallel Distributed Comput., 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
IEEE Trans. Parallel Distributed Syst., 2019
Efficient invisible speculative execution through selective delay and value prediction.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation.
IEEE Trans. Parallel Distributed Syst., 2018
IEEE Trans. Parallel Distributed Syst., 2018
Log. Methods Comput. Sci., 2018
J. Parallel Distributed Comput., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
2017
Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics.
IEEE Trans. Parallel Distributed Syst., 2017
IEEE Trans. Parallel Distributed Syst., 2017
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.
J. Supercomput., 2017
J. Parallel Distributed Comput., 2017
Concurr. Comput. Pract. Exp., 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the International Conference on Supercomputing, 2017
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
IEEE Trans. Parallel Distributed Syst., 2016
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.
J. Supercomput., 2016
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 International Conference on Supercomputing, 2016
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016
Proceedings of the Formal Techniques for Distributed Objects, Components, and Systems, 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
2015
J. Supercomput., 2015
J. Supercomput., 2015
IEEE Trans. Computers, 2015
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence.
ACM Trans. Archit. Code Optim., 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Callback: efficient synchronization without invalidation with a directory just for spin-waiting.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015
Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory.
Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing, 2015
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015
Proceedings of the 11th IEEE International Conference on e-Science, 2015
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2014
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014
2013
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks.
IEEE Trans. Computers, 2013
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 42nd International Conference on Parallel Processing, 2013
Proceedings of the International Conference on Computational Science, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011
Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation.
Proceedings of the International Conference on Parallel Processing, 2011
2010
IEEE Trans. Parallel Distributed Syst., 2010
Proceedings of the 2010 International Conference on High Performance Computing, 2010
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010
2009
Proceedings of the 16th International Conference on High Performance Computing, 2009
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009
2008
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.
J. Parallel Distributed Comput., 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Scalable Directory Organization for Tiled CMP Architectures.
Proceedings of the 2008 International Conference on Computer Design, 2008
2007
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors.
Proceedings of the High Performance Computing, 2007
2006
Proceedings of the Third Conference on Computing Frontiers, 2006
2005
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005