Alberto Ros

Proceedings of the 11th IEEE International Conference on e-Science, 2015

An Efficient, Self-Contained, On-chip Directory: DIR1-SISD.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013

Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.

[BibT_eX]

[DOI]

José L. Abellán

Juan Fernández Peinador

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

A new perspective for efficient virtual-cache coherence.

[BibT_eX]

[DOI]

Stefanos Kaxiras

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 42nd International Conference on Parallel Processing, 2013

Efficient Dir0B Cache Coherency for Many-Core CMPs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2013

2012

Extending Magny-Cours Cache Coherence.

[BibT_eX]

[DOI]

Blas Cuesta Saez

IEEE Trans. Computers, 2012

DAPSCO: Distance-aware partially shared cache organization.

[BibT_eX]

[DOI]

Antonio García-Guirado

ACM Trans. Archit. Code Optim., 2012

Efficient, snoopless, System-on-Chip coherence.

[BibT_eX]

[DOI]

Stefanos Kaxiras

Proceedings of the IEEE 25th International SOC Conference, 2012

Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

ASCIB: adaptive selection of cache indexing bits for removing conflict misses.

[BibT_eX]

[DOI]

Polychronis Xekalakis

Marcelo Cintra

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

PS-Dir: a scalable two-level directory cache.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

Complexity-effective multicore coherence.

[BibT_eX]

[DOI]

Stefanos Kaxiras

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Self-related traces: An alternative to full-system simulation for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation.

[BibT_eX]

[DOI]

Antonio García-Guirado

Proceedings of the International Conference on Parallel Processing, 2011

2010

A Direct Coherence Protocol for Many-Core Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2010

A scalable organization for distributed directories.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

EMC<sup>2</sup>: Extending Magny-Cours coherence for large-scale servers.

[BibT_eX]

[DOI]

Blas Cuesta

Proceedings of the 2010 International Conference on High Performance Computing, 2010

Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

2009

Distance-aware round-robin mapping for large NUCA caches.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High Performance Computing, 2009

Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.

[BibT_eX]

[DOI]

Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009

2008

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2008

DiCo-CMP: Efficient cache coherency in tiled CMP architectures.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Scalable Directory Organization for Tiled CMP Architectures.

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Proceedings of the 2008 International Conference on Computer Design, 2008

2007

Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2007

2006

An efficient cache design for scalable glueless shared-memory multiprocessors.

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[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

2005

A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.

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[DOI]