Alberto Nannarelli

IEEE Access, 2023

Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

2021

Special Section on Scalable Computing for Blockchain Systems.

[BibT_eX]

[DOI]

Hong-Ning Dai Senior

Zibin Zheng

Yan Zhang

Michael Rung-Tsong Lyu

IEEE Trans. Emerg. Top. Comput., 2021

Special Section on "Emerging and Impacting Trends on Computer Arithmetic".

[BibT_eX]

[DOI]

Mioara Joldes

Fabrizio Lamberti

IEEE Trans. Emerg. Top. Comput., 2021

M-PSK Demodulator With Joint Carrier and Timing Recovery.

[BibT_eX]

[DOI]

Daniele Giardino

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

N-Dimensional Approximation of Euclidean Distance.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems.

[BibT_eX]

[DOI]

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019

Tunable Floating-Point Adder.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm.

[BibT_eX]

[DOI]

Sergio Spanò

IEEE Access, 2019

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer.

[BibT_eX]

[DOI]

Marco Matta

IEEE Access, 2019

Fused Multiply-Add for Variable Precision Floating-Point.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Digital Signal Processing Accelerator for RISC-V.

[BibT_eX]

[DOI]

L. Calicchia

V. Ciotoli

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation.

[BibT_eX]

[DOI]

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation.

[BibT_eX]

[DOI]

Marta Franceschi

Maurizio Valle

Proceedings of the 15th International Conference on Synthesis, 2018

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Tunable Floating-Point for Artificial Neural Networks.

[BibT_eX]

[DOI]

Marta Franceschi

Maurizio Valle

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Tunable Floating-Point for Energy Efficient Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

A Power Efficient Digital Front-End for Cognitive Radio Systems.

[BibT_eX]

[DOI]

Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.

[BibT_eX]

[DOI]

Elisardo Antelo

Paolo Montuschi

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Robust throughput boosting for low latency dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A multi-format floating-point multiplier for power-efficient operations.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016

Performance/Power Space Exploration for Binary64 Division Units.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Design and simulation of a quaternary memory cell based on a physical memristor.

[BibT_eX]

[DOI]

Jonathan Taylor

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

A hardware framework for on-chip FPGA acceleration.

[BibT_eX]

[DOI]

Andrea Lomuscio

Proceedings of the International Symposium on Integrated Circuits, 2016

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications.

[BibT_eX]

[DOI]

A. Esposito

Andrea Lomuscio

Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015

Power and Thermal Efficient Numerical Processing.

[BibT_eX]

[DOI]

Proceedings of the Handbook on Data Centers, 2015

Thermal aware floorplanning incorporating temperature dependent wire delay estimation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Characterization of RNS multiply-add units for power efficient DSP.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.

[BibT_eX]

[DOI]

Leonardo Di Carlo

Federico Maria Pandolfi

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015

2014

Guest Editors' Introduction: Special Section on Computer Arithmetic.

[BibT_eX]

[DOI]

Peter-Michael Seidel

Ping Tak Peter Tang

IEEE Trans. Computers, 2014

Decimal engine for energy-efficient multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Energy efficient FPGA based hardware accelerators for financial applications.

[BibT_eX]

[DOI]

Jakob Kenn Toft

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Twenty years of research on RNS for DSP: Lessons learned and future perspectives.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Truncated multipliers through power-gating for degrading precision arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

Power Efficient Division and Square Root Unit.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Comments on 'improving the speed of decimal division'.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Design of power efficient FPGA based hardware accelerators for financial applications.

[BibT_eX]

[DOI]

Jonas Stenbaek Hegner

Joakim Sindholt

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Power efficient design of parallel/serial FIR filters in RNS.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Imprecise arithmetic for low power image processing.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

FPGA Based Acceleration of Decimal Operations.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Temperature dependent wire delay estimation in floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

FPGA implementation of decimal processors for hardware acceleration.

[BibT_eX]

[DOI]

Nicolas Borup

Jonas Dindorp

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Radix-16 Combined Division and Square Root Unit.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010

Post-placement temperature reduction techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Power dissipation challenges in multicore floating-point units.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

On-chip Thermal Modeling Based on SPICE Simulation.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Division Unit for Binary Integer Decimals.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

A variant of a radix-10 combinational multiplier.

[BibT_eX]

[DOI]

Luigi Dadda

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ADAPTO: full-adder based reconfigurable architecture for bit level operations.

[BibT_eX]

[DOI]

Luca Di Nunzio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Session TP8b1: Computer arithmetic II.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

Reducing power dissipation in pipelined accumulators.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

Power dissipation in division.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Low-power adaptive filter based on RNS components.

[BibT_eX]

[DOI]

G. L. Bernocchi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Digit-Recurrence Dividers with Reduced Logical Depth.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

Low-power implementation of polyphase filters in Quadratic Residue Number system.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Power-delay tradeoffs in residue number system.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Power characterization of digital filters implemented on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Fast Radix-4 Retimed Division with Selection by Comparisons.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001

Cached-code compression for energy minimization in embedded processors.

[BibT_eX]

[DOI]

Luca Benini

Alberto Macii

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

FPGA realization of RNS to binary signed conversion architecture.

[BibT_eX]

[DOI]

Roberto Lojacono

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Tradeoffs between residue number system and traditional FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999

Low-Power Divider.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Low-Power Radix-4 Combined Division and Square Root.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998

Power-delay tradeoffs for radix-4 and radix-8 dividers.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Low-power radix-8 divider.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996

Low-power radix-4 divider.

[BibT_eX]

[DOI]