Alberto Macii

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Power-aware partitioning of data converters.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

An integrated thermal estimation framework for industrial embedded platforms.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

J. Embed. Comput., 2009

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Data-Driven Clock Gating for Digital Filters.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Placement-aware Clustering for Integrated Clock and Power Gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Enabling concurrent clock and power gating in an industrial design flow.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Thermal-Aware Design Techniques for Nanometer CMOS Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.

[BibT_eX]

[DOI]

Integr., 2008

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal sleep transistor synthesis under timing and area constraints.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Timing-driven row-based power gating.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.

[BibT_eX]

[DOI]

Antonio Pullini

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal resilient bounded-skew clock tree optimization methodology.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Enabling fine-grain leakage management by voltage anchor insertion.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Low-power embedded systems.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Low-overhead state-retaining elements for low-leakage MTCMOS design.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Memory energy minimization by data compression: algorithms, architectures and implementation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Post-layout leakage power minimization based on distributed sleep transistor insertion.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip.

[BibT_eX]

[DOI]

Kimish Patel

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Scheduling battery usage in mobile systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2003

Discharge Current Steering for Battery Lifetime Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

A Statistic Power Model for Non-synthetic RTL Operators.

[BibT_eX]

[DOI]

Maurizio Bruno

Proceedings of the Integrated Circuit and System Design, 2003

Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Energy-efficient data scrambling on memory-processor interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Increasing the locality of memory access patterns by low-overhead hardware address relocation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A novel architecture for power maskable arithmetic units.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Improving the Efficiency of Memory Partitioning by Address Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Energy-aware design techniques for differential power analysis protection.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Minimizing memory access energy in embedded systems by selective instruction compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Layout-driven memory synthesis for embedded systems-on-chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Discharge current steering for battery lifetime optimization.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

An adaptive data compression scheme for memory traffic minimization in processor-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Enhanced clustered voltage scaling for low power.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Memory design techniques for low energy embedded systems.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-7690-3, 2002

2001

Stream synthesis for efficient power simulation based on spectral transforms.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Discrete-time battery models for system-level low-power design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Battery-Driven Dynamic Power Management.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

Cached-code compression for energy minimization in embedded processors.

[BibT_eX]

[DOI]

Alberto Nannarelli

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Current-controlled policies for battery-driven dynamic power management.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Extending lifetime of portable systems by battery scheduling.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Glitch power minimization by selective gate freezing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Architectures and synthesis algorithms for power-efficient businterfaces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Battery-Driven Dynamic Power Management of Portable Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

A recursive algorithm for low-power memory partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Supporting system-level power exploration for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A Discrete-Time Battery Model for High-Level Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Synthesis of application-specific memories for power optimization in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Selective instruction compression for memory energy reduction in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Peak power constrained test sets: generation heuristics and experiments.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Low-power implementation of a residue-to-weighted conversion unit for a 5-moduli RNS.

[BibT_eX]

[DOI]