Alberto L. Sangiovanni-Vincentelli

Proceedings of the conference on European design automation, 1992

An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints.

[BibT_eX]

[DOI]

Eric Felt

Edoardo Charbon

Enrico Malavasi

Proceedings of the conference on European design automation, 1992

Communication based logic partitioning.

[BibT_eX]

[DOI]

Mark Beardslee

Bill Lin

Proceedings of the conference on European design automation, 1992

On the Temporal Equivalence of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

An Improved Synthesis Algorithm for Multiplexor-Based PGA's.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Solving the State Assignment Problem for Signal Transition Graphs.

[BibT_eX]

[DOI]

Luciano Lavagno

Cho W. Moon

Proceedings of the 29th Design Automation Conference, 1992

Automatic Reduction in CTL Compositional Model Checking.

[BibT_eX]

[DOI]

Thomas R. Shiple

Massimiliano Chiodo

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

A Verification Strategy for Timing-Constrained Systems.

[BibT_eX]

[DOI]

Felice Balarin

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991

A massively parallel algorithm for three-dimensional device simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Retiming and resynthesis: optimizing sequential networks with combinational techniques.

[BibT_eX]

[DOI]

Ellen M. Sentovich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Reduced offsets for minimization of binary-valued functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A macromodeling algorithm for analog circuits.

[BibT_eX]

[DOI]

Giorgio Casinovi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Editor's Foreword.

[BibT_eX]

[DOI]

Algorithmica, 1991

A Theoretical Framework for Simulated Annealing.

[BibT_eX]

[DOI]

Fabio Romeo

Algorithmica, 1991

Learning Concepts by Synthesizing Minimal Threshold Gate Networks.

[BibT_eX]

[DOI]

Arlindo L. Oliveira

Proceedings of the Eighth International Workshop (ML91), 1991

Retiming of Circuits with Single Phase Transparent Latches.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate Networks.

[BibT_eX]

[DOI]

Arlindo L. Oliveira

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Clustering for Minimum Delay/Area.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Enhancement through the Generalized Bypass Transform.

[BibT_eX]

[DOI]

Patrick C. McGeer

Sartaj Sahni

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Behavioral Representation for Nyquist Rate A/D Converters.

[BibT_eX]

[DOI]

Edward W. Y. Liu

Georges G. E. Gielen

Paul R. Gray

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Testability Solutions: Who Really Wants Them? (Panel Abstract).

[BibT_eX]

Proceedings of the 28th Design Automation Conference, 1991

A Framework for Satisfying Input and Output Encoding Constraints.

[BibT_eX]

[DOI]

Tiziano Villa

Proceedings of the 28th Design Automation Conference, 1991

Algorithms for Synthesis of Hazard-Free Asynchronous Circuits.

[BibT_eX]

[DOI]

Luciano Lavagno

Kurt Keutzer

Proceedings of the 28th Design Automation Conference, 1991

1990

NOVA: state assignment of finite state machines for optimal two-level logic implementation.

[BibT_eX]

[DOI]

Tiziano Villa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

'Zone-refining' techniques for IC layout compaction.

[BibT_eX]

[DOI]

Hyunchul Shin

Carlo H. Séquin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Irredundant sequential machines via optimal logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Multilevel logic synthesis.

[BibT_eX]

[DOI]

Proc. IEEE, 1990

Implicit State Enumeration of Finite State Machines Using BDDs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Timing Optimization with Testability Considerations.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Optimal Test Set Design for Analog Circuits.

[BibT_eX]

[DOI]

Linda Milor

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Computing Parametric Yield Accurately and Efficiently.

[BibT_eX]

[DOI]

Linda Milor

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Performance Optimization of Pipelined Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Routing Methodology for Analog Integrated Circuits.

[BibT_eX]

[DOI]

Enrico Malavasi

Umakanta Choudhury

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.

[BibT_eX]

[DOI]

Luciano Lavagno

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

CADICS - Cyclic Analog-to-Digital Converter Synthesis.

[BibT_eX]

[DOI]

Gani Jusuf

Paul R. Gray

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Heuristic Algorithm for the Fanout Problem.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Testing Strategies for the 1990's (Panel Abstract).

[BibT_eX]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Logic Synthesis for Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Reduced Offsets for Two-Level Multi-Valued Logic Minimization.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Constraint Generation for Routing Analog Circuits.

[BibT_eX]

[DOI]

Umakanta Choudhury

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Design Management Based on Design Traces.

[BibT_eX]

[DOI]

Andrea Casotto

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Steady-state methods for simulating analog and microwave circuits.

[BibT_eX]

Jacob K. White

The Kluwer international series in engineering and computer science 94, Kluwer, ISBN: 978-0-7923-9069-5, 1990

1989

A mixed frequency-time approach for distortion analysis of switching filter circuits.

[BibT_eX]

[DOI]

Jacob White

IEEE J. Solid State Circuits, April, 1989

Boolean decomposition in multilevel logic optimization.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, April, 1989

Comments on 'Simulation of nonlinear circuits in the frequency domain' [with reply].

[BibT_eX]

[DOI]

George W. Rhyne

Michael Steer

K. S. Kundent

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Logic verification algorithms and their parallel implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A synthesis and optimization procedure for fully and easily testable sequential machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Design Methods and Tools for Application Specific Integrated Circuits.

[BibT_eX]

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

Logic minimization for factored forms.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Timing Analysis in a Logic Synthesis Environment.

[BibT_eX]

[DOI]

Nicholas Weiner

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations.

[BibT_eX]

[DOI]

Tiziano Villa

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Multi-level Logic Simplification Using Don't Cares and Filters.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

ORCA a Sea-of-Gates Place and Route System.

[BibT_eX]

[DOI]

Mitsuru Igusa

Mark Beardslee

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Optimization-based transistor sizing.

[BibT_eX]

[DOI]

Jyuo-Min Shyu

John P. Fishburn

Alfred E. Dunlop

IEEE J. Solid State Circuits, April, 1988

ThunderBird: a complete standard cell layout package.

[BibT_eX]

[DOI]

Carl Sechen

Douglas Braun

IEEE J. Solid State Circuits, April, 1988

DELIGHT.SPICE: an optimization-based system for the design of integrated circuits.

[BibT_eX]

[DOI]

William Nye

David C. Riley

André L. Tits

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Test generation for sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Three-dimensional capacitance evaluation on a Connection Machine.

[BibT_eX]

[DOI]

Roberto Guerrieri

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A new aggregation technique for the solution of large systems of algebraic equations [IC simulation].

[BibT_eX]

[DOI]

Giorgio Casinovi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Techniques for multilayer channel routing.

[BibT_eX]

[DOI]

Douglas Braun

Jeffrey L. Burns

Fabio Romeo

Kartikeya Mayaram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Multi-level logic minimization using implicit don't cares.

[BibT_eX]

[DOI]

Christopher R. Morrison

Richard L. Rudell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Efficient Parallel Learning Algorithms for Neural Networks.

[BibT_eX]

[DOI]

Alan H. Kramer

Proceedings of the Advances in Neural Information Processing Systems 1, 1988

Optimal Logic Synthesis and Testability : Two Sides of the Same Coin.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

An Incomplete Scan Design Approach to Test Generation for Sequential Machines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

Timing optimization of combinational logic.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

ECSTASY: a new environment for IC design optimization.

[BibT_eX]

[DOI]

Jyuo-Min Shyu

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Logic verification using binary decision diagrams in a logic synthesis environment.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A modified approach to two-level logic minimization.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A band relaxation algorithm for reliable and parallelizable circuit simulation.

[BibT_eX]

[DOI]

Andrew Lumsdaine

Jacob White

Donald M. Webber

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

An envelope-following method for the efficient transient simulation of switching power and filter circuits.

[BibT_eX]

[DOI]

Jacob White

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

MulCh: a multi-layer channel router using one, two, and three layer partitions.

[BibT_eX]

[DOI]

Ronald I. Greenberg

Alexander T. Ishii

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Boolean decomposition in multi-level logic optimization.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

A Detailed Router Based on Incremental Routing Modifications: Mighty.

[BibT_eX]

[DOI]

Hyunchul Shin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Multiple-Valued Minimization for PLA Optimization.

[BibT_eX]

[DOI]

Richard L. Rudell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells.

[BibT_eX]

[DOI]

Andrea Casotto

Fabio Romeo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

MIS: A Multiple-Level Logic Optimization System.

[BibT_eX]

[DOI]

Richard L. Rudell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

CAD tools for ASIC design.

[BibT_eX]

[DOI]

Arthur R. Newton

Proc. IEEE, 1987

Circuit Simulation on the Connection Machine.

[BibT_eX]

[DOI]

Donald M. Webber

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

PLATYPUS: A PLA Test Pattern Generation Tool.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Models for a New Profit-Based Methodology for Statistical Design of Integrated Circuits.

[BibT_eX]

[DOI]

David C. Riley

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Correction to "Optimal State Assignment for Finite State Machines".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Simulation of Nonlinear Circuits in the Frequency Domain.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Computer-Aided Design for VLSI Circuits.

[BibT_eX]

[DOI]

Computer, 1986

New Front-End and Line Justification Algorithm for Automatic Test Generation.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1986, 1986

PROTEUS : A Logic Verification System for Combinational Circuits.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1986, 1986

Highlights of VLSI Research at Berkeley.

[BibT_eX]

Carlo H. Séquin

Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

Two-dimensional compaction by "zone refining".

[BibT_eX]

[DOI]

Hyunchul Shin

Carlo H. Séquin

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

TimberWolf3.2: a new standard cell placement and global routing package.

[BibT_eX]

[DOI]

Carl Sechen

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Floor planning systems (panel session).

[BibT_eX]

[DOI]

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Mixed-level fault coverage estimation.

[BibT_eX]

[DOI]

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Chameleon: a new multi-layer channel router.

[BibT_eX]

[DOI]

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

A New Symbolic Channel Router: YACR2.

[BibT_eX]

[DOI]

James Reed

Mauro Santomauro

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

Optimal State Assignment for Finite State Machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

Design Aids for VLSI: A Perspective Revisited.

[BibT_eX]

[DOI]

Donald O. Pederson

IEEE Des. Test, 1985

1984

A Computational Approach for the Diagnosability of Dynamical Circuits.

[BibT_eX]

[DOI]

V. Visvanathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Relaxation-Based Electrical Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Logic Minimization Algorithms for VLSI Synthesis

[BibT_eX]

[DOI]

Curtis T. McMullen

The Kluwer International Series in Engineering and Computer Science 2, Springer, ISBN: 978-1-4613-2821-6, 1984

1983

Solution of piecewise-linear ordinary differential equations using waveform relaxation and laplace transforms.

[BibT_eX]

[DOI]

R. John Kaye

IEEE Trans. Syst. Man Cybern., 1983

Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays.

[BibT_eX]

[DOI]

Proceedings of the 20th Design Automation Conference, 1983

1982

The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits.

[BibT_eX]

[DOI]

Ekachai Lelarasmee

Albert E. Ruehli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982

An Algorithm for Optimal PLA Folding.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982

Computer-aided design via optimization : A review.

[BibT_eX]

[DOI]

David Q. Mayne

Elijah Polak

Autom., 1982

VICTOR : A Fast VLSI Testability Analysis Program.

[BibT_eX]

Ion M. Ratiu

Donald O. Pederson

Proceedings of the Proceedings International Test Conference 1982, 1982

Relax: A new circuit for large scale MOS integrated circuits.

[BibT_eX]

[DOI]

Ekachai Lelarasmee

Proceedings of the 19th Design Automation Conference, 1982

Techniques for programmable logic array folding.

[BibT_eX]

[DOI]

Proceedings of the 19th Design Automation Conference, 1982

1981

Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case.

[BibT_eX]

[DOI]

V. Visvanathan

IEEE Trans. Computers, 1981

Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems.

[BibT_eX]

[DOI]

Richard Saeks

V. Visvanathan

IEEE Trans. Computers, 1981

1978

A new shortest path updating algorithm.

[BibT_eX]

[DOI]

S. Goto

Networks, 1978

1973

State-Space Approach in Problem-solving Optimization.

[BibT_eX]

[DOI]