Alberto Ghiribaldi
According to our database1,
Alberto Ghiribaldi
authored at least 13 papers
between 2011 and 2021.
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Bibliography
2021
IEEE Micro, 2021
2014
Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs.
PhD thesis, 2014
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems.
Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 2012 International Green Computing Conference, 2012
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011