Alberto Cestero
According to our database1,
Alberto Cestero
authored at least 9 papers
between 2005 and 2021.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2021
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018
2016
IEEE J. Solid State Circuits, 2016
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2013
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.
IEEE J. Solid State Circuits, 2013
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM.
IEEE J. Solid State Circuits, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2005
IEEE J. Solid State Circuits, 2005