Alberto A. Del Barrio
Orcid: 0000-0002-6769-1200Affiliations:
- Complutense University of Madrid, Spain
According to our database1,
Alberto A. Del Barrio
authored at least 67 papers
between 2008 and 2024.
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Bibliography
2024
Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing.
IEEE Trans. Computers, June, 2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Digit. Signal Process., 2024
Differential evolution VQE for crypto-currency arbitrage. Quantum optimization with many local minima.
Digit. Signal Process., 2024
Neuromorphic Circuit Simulation with Memristors: Design and Evaluation Using MemTorch for MNIST and CIFAR.
CoRR, 2024
Proceedings of the IEEE International Conference on Acoustics, 2024
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers.
Proceedings of the Next Generation Arithmetic - 4th International Conference, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
CTMQ: Cyclic Training of Convolutional Neural Networks with Multiple Quantization Steps.
CoRR, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
Proceedings of the Next Generation Arithmetic - Third International Conference, 2022
Proceedings of the Annual Modeling and Simulation Conference, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
CoRR, 2021
A Cost-Efficient Approximate Dynamic Ranged Multiplication and Approximation-Aware Training on Convolutional Neural Networks.
IEEE Access, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
Multim. Tools Appl., 2020
Digit. Signal Process., 2020
Comput. Ind., 2020
CNN Inference acceleration using low-power devices for human monitoring and security scenarios.
Comput. Electr. Eng., 2020
Efficient embedding and retrieval of information for high-resolution videos coded with HEVC.
Comput. Electr. Eng., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Computers, 2019
CoRR, 2019
SMURF: Systematic Methodology for Unveiling Relevant Factors in Retrospective Data on Chronic Disease Treatments.
IEEE Access, 2019
A study on the parallelization of moeas to predict the patient's response to the onabotulinumtoxina treatment.
Proceedings of the 2019 Summer Simulation Conference, 2019
Proceedings of the 2019 Summer Simulation Conference, 2019
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019
A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
Fast and effective CU size decision based on spatial and temporal homogeneity detection.
Multim. Tools Appl., 2018
Complexity reduction in the HEVC/H265 standard based on smooth region classification.
Digit. Signal Process., 2018
Proceedings of the 50th Computer Simulation Conference, 2018
Proceedings of the 50th Computer Simulation Conference, 2018
Proceedings of the 22nd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2018
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Support System to Improve Reading Activity in Parkinson's Disease and Essential Tremor Patients.
Sensors, 2017
A DCT and neural network based system to obtain the characteristics of biological images.
Proceedings of the Summer Simulation Multi-Conference, 2017
Simulation and implementation of a low-cost platform to improve the quality of biological images.
Proceedings of the Summer Simulation Multi-Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Proceedings of the Summer Computer Simulation Conference, 2016
Proceedings of the Real-Time Image and Video Processing 2016, 2016
2014
ACM Trans. Embed. Comput. Syst., 2014
Improving circuit performance with multispeculative additive trees in high-level synthesis.
Microelectron. J., 2014
Digit. Signal Process., 2014
2013
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Integr., 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
2011
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE Des. Test Comput., 2009
2008
Proceedings of the 26th International Conference on Computer Design, 2008
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008