Albert R. Wang

According to our database, Albert R. Wang authored at least 16 papers between 1987 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2001

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.

Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1998

Code Optimization Techniques in Embedded DSP Microprocessors.

Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang

Des. Autom. Embed. Syst., 1998

1996

Storage Assignment to Decrease Code Size.

Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang

ACM Trans. Program. Lang. Syst., 1996

1995

A Design and Validation System for Asynchronous Circuits.

Peter Vanbekbergen, Albert R. Wang, Kurt Keutzer

Proceedings of the 32st Conference on Design Automation, 1995

1994

Verification of asynchronous interface circuits with bounded wire delays.

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang

J. VLSI Signal Process., 1994

Certified timing verification and the transition delay of a logic circuit.

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang

IEEE Trans. Very Large Scale Integr. Syst., 1994

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Challenges in code generation for embedded processors.

Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993

Computation of floating mode delay in combinational circuits: practice and implementation.

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1989

Boolean decomposition in multilevel logic optimization.

Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli

IEEE J. Solid State Circuits, April, 1989

Multi-level Logic Simplification Using Don't Cares and Filters.

Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Multi-level logic minimization using implicit don't cares.

Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Timing optimization of combinational logic.

Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Logic verification using binary decision diagrams in a logic synthesis environment.

Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Boolean decomposition in multi-level logic optimization.

Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

MIS: A Multiple-Level Logic Optimization System.

Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987