Albert Martinez
According to our database1,
Albert Martinez
authored at least 4 papers
between 2006 and 2010.
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Bibliography
2010
Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Comput. Sci., 2010
2006
Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006