Albert Magyar

Orcid: 0000-0002-4218-3824

According to our database1, Albert Magyar authored at least 6 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.
IEEE Micro, 2021

2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes.
Proceedings of the International Conference on Computer-Aided Design, 2019

2017
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Cyclist: Accelerating hardware development.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017


  Loading...