Albert J. Ou

Orcid: 0000-0001-7528-7200

According to our database1, Albert J. Ou authored at least 10 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.
CoRR, 2019

2017

2015
Single-chip microprocessor that communicates directly using light.
Nat., 2015


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