Alan P. Smith

According to our database, Alan P. Smith authored at least 6 papers between 2002 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2013

The Next Generation 64b SPARC Core in a T4 SoC Processor.

Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

IEEE J. Solid State Circuits, 2013

2012

The next-generation 64b SPARC core in a T4 SoC processor.

Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 40 nm 16-Core 128-Thread SPARC SoC Processor.

Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway W. Tam, Alan P. Smith, Ha Pham, Hongping Penny Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong

IEEE J. Solid State Circuits, 2011

2010

A 40nm 16-core 128-thread CMT SPARC SoC processor.

Jinuk Luke Shin, Kenway W. Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Penny Li, Alan P. Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2002

Implementation of a third-generation 1.1-GHz 64-bit microprocessor.

Georgios K. Konstadinidis, Kevin Normoyle, Samson Wong, Sutikshan Bhutani, Harry Stuimer, Timothy Johnson, Alan P. Smith, Daniel Y. Cheung, Fabrizio Romano, Shifeng Yu, Sung-Hun Oh, Victor Melamed, Sridhar Narayanan, David Bunsey, Cong Khieu, Kevin J. Wu, Ralf Schmitt, Andy Dumlao, Massimo Sutera, Jade Chau, K. James Lin, William S. Coates

IEEE J. Solid State Circuits, 2002