Alan J. Hu

Orcid: 0000-0002-4276-0169

According to our database1, Alan J. Hu authored at least 89 papers between 1986 and 2024.

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Bibliography

2024
DRAT Proofs of Unsatisfiability for SAT Modulo Monotonic Theories.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

2023
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators.
ACM Trans. Embed. Comput. Syst., 2023

2022
Gridiron: A Technique for Augmenting Cloud Workloads with Network Bandwidth Requirements.
CoRR, 2022

CoSpot: a cooperative VM allocation framework for increased revenue from spot instances.
Proceedings of the 13th Symposium on Cloud Computing, SoCC 2022, 2022

2020
Scalable constraint-based virtual data center allocation.
Artif. Intell., 2020

2019

2018
VNF chain abstraction for cloud service providers.
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018

VNF chain allocation and management at data center scale.
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018

2017
Scalable Constraint-based Virtual Data Center Allocation.
Proceedings of the Twenty-Sixth International Joint Conference on Artificial Intelligence, 2017

2016
Scalable, high-quality, SAT-based multi-layer escape routing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Precisely Measuring Quantitative Information Flow: 10K Lines of Code and Beyond.
Proceedings of the IEEE European Symposium on Security and Privacy, 2016

Fast, Flexible, and Minimal CTL Synthesis via SMT.
Proceedings of the Computer Aided Verification - 28th International Conference, 2016

2015
Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

SAT Modulo Monotonic Theories.
Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, 2015

2014
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.
ACM Trans. Design Autom. Electr. Syst., 2014

Panel: Future SoC verification methodology: UVM evolution or revolution?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.
IEEE Trans. Computers, 2013

Proving termination of nonlinear command sequences.
Formal Aspects Comput., 2013

Efficient modular SAT solving for IC3.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

2012
Formal-Analysis-Based Trace Computation for Post-Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Single-Solver Algorithms for 2QBF - (Poster Presentation).
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Emulation in post-silicon validation: It's not just for functionality anymore.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Lazy suspect-set computation: fault diagnosis for deep electrical bugs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces.
Proceedings of the Computer Aided Verification - 24th International Conference, 2012

2011
Preface.
Int. J. Softw. Tools Technol. Transf., 2011

Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Less Haste, Less Waste: On Recycling and Its Limits in Strand Displacement Systems.
Proceedings of the DNA Computing and Molecular Programming - 17th International Conference, 2011

TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead.
Proceedings of the 48th Design Automation Conference, 2011

2010
Context-Bounded Translations for Concurrent Software: An Empirical Evaluation.
Proceedings of the Model Checking Software, 2010

Special Session on Debugging.
Proceedings of the Hardware and Software: Verification and Testing, 2010

Bridging pre-silicon verification and post-silicon validation.
Proceedings of the 47th Design Automation Conference, 2010

2009
Approximating the safely reusable set of learned facts.
Int. J. Softw. Tools Technol. Transf., 2009

A Scalable Memory Model for Low-Level Code.
Proceedings of the Verification, 2009

2008
BackSpace: Moving Towards Reality.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Automatic Inference of Frame Axioms Using Static Analysis.
Proceedings of the 23rd IEEE/ACM International Conference on Automated Software Engineering (ASE 2008), 2008

Calysto: scalable and precise extended static checking.
Proceedings of the 30th International Conference on Software Engineering (ICSE 2008), 2008

BackSpace: Formal Analysis for Post-Silicon Debug.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007
An Inference-Rule-Based Decision Procedure for Verification of Heap-Manipulating Programs with Mutable Data and Cyclic Data Structures.
Proceedings of the Verification, 2007

Proving Termination by Divergence.
Proceedings of the Fifth IEEE International Conference on Software Engineering and Formal Methods (SEFM 2007), 2007

Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless.
Proceedings of the Hardware and Software: Verification and Testing, 2007

Exploiting Shared Structure in Software Verification Conditions.
Proceedings of the Hardware and Software: Verification and Testing, 2007

Boosting Verification by Automatic Tuning of Decision Procedures.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

An Effective Guidance Strategy for Abstraction-Guided Simulation.
Proceedings of the 44th Design Automation Conference, 2007

Verification Coverage: When is Enough, Enough?
Proceedings of the 44th Design Automation Conference, 2007

Structural Abstraction of Software Verification Conditions.
Proceedings of the Computer Aided Verification, 19th International Conference, 2007

Verifying Heap-Manipulating Programs in an SMT Framework.
Proceedings of the Automated Technology for Verification and Analysis, 2007

2006
B-Cubing: New Possibilities for Efficient SAT-Solving.
IEEE Trans. Computers, 2006

System-on-Chip: Reuse and Integration.
Proc. IEEE, 2006

Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.
Int. J. Parallel Program., 2006

Panel: Assertion-Based Verification -What's the Big Deal?
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.
Proceedings of the 43rd Design Automation Conference, 2006

EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation.
Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005
Empirically Efficient Verification for a Class of Infinite-State Systems.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

Improving Multiple-CMP Systems Using Token Coherence.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

B-cubing theory: new possibilities for efficient SAT-solving.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Cutpoints for formal equivalence verification of embedded software.
Proceedings of the EMSOFT 2005, 2005

Efficient SAT solving: beyond supercubes.
Proceedings of the 42nd Design Automation Conference, 2005

Partitioned model checking from software specifications.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Integration of supercubing and learning in a SAT solver.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Fixing Races for Fun and Profit: How to Use access(2).
Proceedings of the 13th USENIX Security Symposium, August 9-13, 2004, San Diego, CA, USA, 2004

Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003
Automatable Verification of Sequential Consistency.
Theory Comput. Syst., 2003

Toward a decidable notion of sequential consistency.
Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

Efficient Generation of Monitor Circuits for GSTE Assertion Graphs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Reasoning about GSTE Assertion Graphs.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002
Automatic formal verification for scheduled VLIW code.
Proceedings of the 2002 Joint Conference on Languages, 2002

High-Level specification and automatic generation of IP interface monitors.
Proceedings of the 39th Design Automation Conference, 2002

Semi-formal Bounded Model Checking.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Fast Specification of Cycle-accurate Processor Models.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Proving sequential consistency by model checking.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Register Transformations with Multiple Clock Domains.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Source-Level Transformations for Improved Formal Verification.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Monitor-Based Formal Specification of PCI.
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Automatic formal verification of DSP software.
Proceedings of the 37th Conference on Design Automation, 2000

1999
SPUDD: Stochastic Planning using Decision Diagrams.
Proceedings of the UAI '99: Proceedings of the Fifteenth Conference on Uncertainty in Artificial Intelligence, Stockholm, Sweden, July 30, 1999

Model-Checking a Secure Gorup Communication Protocol: A Case Study.
Proceedings of the Formal Methods for Protocol Engineering and Distributed Systems, 1999

1998
BDDNOW: A Parallel BDD Package.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.
Proceedings of the Applied Formal Methods, 1998

Approximate Reachability with BDDs Using Overlapping Projections.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Formal Verification of the HAL S1 System Cache Coherence Protocol.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1994
New Techniques for Efficient Verification with Implicitly Conjoined BDDs.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Reducing BDD Size by Exploiting Functional Dependencies.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Efficient Verification with BDDs using Implicitly Conjoined Invariants.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992
Protocol Verification as a Hardware Design Aid.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Higher-Level Specification and Verification with BDDs.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991
Checking for Language Inclusion Using Simulation Preorders.
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

1986
Selection of the optimum uniform partition search.
Computing, 1986


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