Alan J. Drake

According to our database1, Alan J. Drake authored at least 19 papers between 2000 and 2015.

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Bibliography

2015
Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Optimization and modeling of resonant clocking inductors for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability.
IEEE Micro, 2013

Runtime power reduction capability of the IBM POWER7+ chip.
IBM J. Res. Dev., 2013

Innovative practices session 7C: Self-calibration & trimming.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
Voltage droop reduction using throttling controlled by timing margin feedback.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Introducing the Adaptive Energy Management Features of the Power7 Chip.
IEEE Micro, 2011

Active management of timing guardband to save energy in POWER7.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
Adaptive energy management features of the POWER7TM processor.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2007
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
Resonant clocking using distributed parasitic capacitance.
IEEE J. Solid State Circuits, 2004

2003
Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Resonant clocking using distributed parasitic capacitance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications.
Proceedings of the 38th Design Automation Conference, 2001

2000
A microprocessor design project in an introductory VLSI course.
IEEE Trans. Educ., 2000

CGaAs PowerPC FXU.
Proceedings of the 37th Conference on Design Automation, 2000


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