Alak Majumder
Orcid: 0000-0003-4775-8591
According to our database1,
Alak Majumder
authored at least 37 papers
between 2015 and 2024.
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Bibliography
2024
Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient.
J. Circuits Syst. Comput., September, 2024
Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system.
Peer Peer Netw. Appl., May, 2024
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Integr., 2023
Proceedings of the 33rd International Conference Radioelektronika, 2023
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.
Proceedings of the 33rd International Conference Radioelektronika, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current.
J. Circuits Syst. Comput., 2022
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.
Integr., 2022
2021
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time.
Circuits Syst. Signal Process., 2021
2020
Microelectron. J., 2020
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020
Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020
2019
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
J. Circuits Syst. Comput., 2019
2018
J. Circuits Syst. Comput., 2018
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.
J. Circuits Syst. Comput., 2018
CoRR, 2018
2017
A 65 nm Design of 0.6 V/8.98 <i>μ</i>W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications.
J. Low Power Electron., 2017
J. Low Power Electron., 2017
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit.
Integr., 2017
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect.
Integr., 2017
Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect.
Turkish J. Electr. Eng. Comput. Sci., 2017
Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users.
IEEE Consumer Electron. Mag., 2017
Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment.
IEEE Consumer Electron. Mag., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
A 90 nm leakage control transistor based clock gating for low power flip flop applications.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2015
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs.
Proceedings of the 16th Latin-American Test Symposium, 2015
Development of a prototype to detect speed limit violation for better traffic management.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015