Alain J. Martin

Affiliations:
  • California Institute of Technology, Pasadena, CA, USA


According to our database1, Alain J. Martin authored at least 60 papers between 1978 and 2022.

Collaborative distances:
  • Dijkstra number2 of one.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
On-the-Fly Garbage Collection: An Exercise in Cooperation.
Proceedings of the Edsger Wybe Dijkstra: His Life, Work, and Legacy, 2022

2015
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2009
Asynchronous logic for high variability nano-CMOS.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Asynchronous Nano-Electronics: Preliminary Investigation.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Analog and asynchronous variation-aware circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Asynchronous Techniques for System-on-Chip Design.
Proc. IEEE, 2006

Can Asynchronous Techniques Help the SoC Designer?
Proceedings of the IFIP VLSI-SoC 2006, 2006

Slack Matching Quasi Delay-Insensitive Circuits.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
SEU-Tolerant QDI Circuits.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
An Eight-Bit Divider Implemented in Asynchronous Pulse Logic.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Three Generations of Asynchronous Microprocessors.
IEEE Des. Test Comput., 2003

An architecture for asynchronous FPGAs.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

High-level synthesis of asynchronous systems by data-driven decomposition.
Proceedings of the 40th Design Automation Conference, 2003

The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Transistor sizing of energy-delay--efficient circuits.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Energy-delay efficiency of VLSI computations.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.
Proceedings of the 2002 Design, 2002

2001
Towards an energy complexity of computation.
Inf. Process. Lett., 2001

Data-driven process decomposition for circuit synthesis.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Precise Exceptions in Asynchronous Processors.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1999
Projection: A Synthesis Technique for Concurrent Systems.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Slack Elasticity in Concurrent Computing.
Proceedings of the Mathematics of Program Construction, 1998

1997
The Design of an Asynchronous MIPS R3000 Microprocessor.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Specifying the Caltech Asynchronous Microprocessor.
Sci. Comput. Program., 1996

A program transformation approach to asynchronous VLSI design.
Proceedings of the NATO Advanced Study Institute on Deductive Program Design, 1996

The energy and entropy of VLSI computations.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
An Action System Specification of the Caltech Asynchronous Microprocessor.
Proceedings of the Mathematics of Program Construction, 1995

1994
A 100-MIPS GaAs Asynchronous Microprocessor.
IEEE Des. Test Comput., 1994

Low-energy asynchronous memory design.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

An asynchronous pipelined lattice structure filter.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Design of a delay-insensitive multiply-accumulate unit.
Integr., 1993

1992
Asynchronous Datapaths and the Design of an Asynchronous Adder.
Formal Methods Syst. Des., 1992

Translating Concurrent Programs into VLSI Chips.
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

Tomorrow's Digital Hardware will be Asynchronous and Verified.
Proceedings of the Algorithms, Software, Architecture, 1992

1990
An Interconnection Network for Distributed Recursive Computations.
IEEE Trans. Computers, 1990

Distributed Sorting.
Sci. Comput. Program., 1990

1989
The design of an asynchronous microprocessor.
SIGARCH Comput. Archit. News, 1989

The first asynchronous microprocessor: the test results.
SIGARCH Comput. Archit. News, 1989

An Algorithm for Transitive Reduction of an Acyclic Graph.
Sci. Comput. Program., 1989

The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation.
Proceedings of the Hardware Specification, 1989

1988
The architecture and programming of the Ametek series 2010 multicomputer.
Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988

A message-passing model for highly concurrent computation.
Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988

1986
A New Generalization of Dekker's Algorithm for Mutual Exclusion.
Inf. Process. Lett., 1986

Compiling Communicating Processes Into Delay-Insensitive VLSI Circuits.
Distributed Comput., 1986

The Sync Model: A Parallel Execution Method for Logic Programming.
Proceedings of the 1986 Symposium on Logic Programming, 1986

The Sneptree : A Versatile Interconnection Network.
Proceedings of the International Conference on Parallel Processing, 1986

1985
Distributed Mutual Exclusion on a Ring of Processes.
Sci. Comput. Program., 1985

Fair Mutual Exclusion with Unfair P and V Operations.
Inf. Process. Lett., 1985

The Probe: An Addition to Communication Primitives.
Inf. Process. Lett., 1985

1984
On David Gries's plateau problem.
ACM SIGSOFT Softw. Eng. Notes, 1984

A Presentation of the Fibonacci Algorithm.
Inf. Process. Lett., 1984

1983
A Characterization of Product-Form Queuing Networks
J. ACM, April, 1983

Verteilte Ausführung rekursiver Algorithmen auf Gittern von Prozessoren.
Elektron. Rechenanlagen, 1983

A General Proof Rule for Procedures in Predicate Transformer Semantics.
Acta Informatica, 1983

1981
An Axiomatic Definition of Synchronization Primitives.
Acta Informatica, 1981

1980
A Distributed Implementation Method for Parallel Programming.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980

1979
Two Implementations of the Conditional Critical Region Using a Split Binary Semaphore.
Inf. Process. Lett., 1979

1978
On-the-Fly Garbage Collection: An Exercise in Cooperation.
Commun. ACM, 1978


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