Alain J. Martin
Affiliations:- California Institute of Technology, Pasadena, CA, USA
According to our database1,
Alain J. Martin
authored at least 60 papers
between 1978 and 2022.
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On csauthors.net:
Bibliography
2022
Proceedings of the Edsger Wybe Dijkstra: His Life, Work, and Legacy, 2022
2015
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2004
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
Proceedings of the Mathematics of Program Construction, 1998
1997
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1996
A program transformation approach to asynchronous VLSI design.
Proceedings of the NATO Advanced Study Institute on Deductive Program Design, 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
Proceedings of the Mathematics of Program Construction, 1995
1994
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
1993
1992
Formal Methods Syst. Des., 1992
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992
Tomorrow's Digital Hardware will be Asynchronous and Verified.
Proceedings of the Algorithms, Software, Architecture, 1992
1990
IEEE Trans. Computers, 1990
1989
SIGARCH Comput. Archit. News, 1989
Sci. Comput. Program., 1989
The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation.
Proceedings of the Hardware Specification, 1989
1988
Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988
Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, 1988
1986
Inf. Process. Lett., 1986
Distributed Comput., 1986
The Sync Model: A Parallel Execution Method for Logic Programming.
Proceedings of the 1986 Symposium on Logic Programming, 1986
The Sneptree : A Versatile Interconnection Network.
Proceedings of the International Conference on Parallel Processing, 1986
1985
1984
1983
Verteilte Ausführung rekursiver Algorithmen auf Gittern von Prozessoren.
Elektron. Rechenanlagen, 1983
Acta Informatica, 1983
1981
1980
A Distributed Implementation Method for Parallel Programming.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980
1979
Two Implementations of the Conditional Critical Region Using a Split Binary Semaphore.
Inf. Process. Lett., 1979
1978