Alain Guyot

According to our database1, Alain Guyot authored at least 31 papers between 1971 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

1999
A Dedicated Circuit for Charged Particles Simulation Using the Monte Carlo Method.
J. VLSI Signal Process., 1999

1998
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard.
IEEE Trans. Very Large Scale Integr. Syst., 1998

New Svoboda-Tung Division.
IEEE Trans. Computers, 1998

Guest Editorial.
IEEE J. Solid State Circuits, 1998

A new low-power GaAs two-single-port memory cell.
IEEE J. Solid State Circuits, 1998

3D CMOS SOL for high performance computing.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
A dedicated circuit for charged particles simulation using the Monte Carlo method.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider.
IEEE J. Solid State Circuits, 1996

Self timed division and square-root extraction.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

FPGA Design Migration: Some Remarks.
Proceedings of the Field-Programmable Logic, 1996

Asynchronous SRT Dividers: The Real Cost.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
SAGA: the first general-purpose on-line arithmetic co-processor.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Svoboda-Tung division with no compensation.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Application of fast layout synthesis environment to dividers evaluation.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

Analytic approach for error masking elimination in on-line multipliers.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
Design for testability of on-line multipliers.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Combinational Digit-Set Converters for Hybrid Radix-4 Arithmetic.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A VLSI Implementation of Parallel Fast Fourier Transform.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Design of an On-Line Euclidean Processor.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functions.
Proceedings of the VLSI 93, 1993

Design of a GaAs redundant divider.
Proceedings of the VLSI 93, 1993

VLSI Design of On-Line Add/Multiply Algorithms.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1991
OCAPI: A Prototype for High Precision Arithmetic.
Proceedings of the VLSI 91, 1991

OCAPI: architecture of a VLSI coprocessor for the GCD and the extended GCD of large numbers.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1989
JANUS, an on-line multiplier/divider for manipulating large numbers.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1987
A Way to Build Efficient Carry-Skip Adders.
IEEE Trans. Computers, 1987

The FELIN arithmetic coprocessor chip.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1975
Un compilateur de microprogrammes.
PhD thesis, 1975

1971
CASSANDRE and the Computer Aided Logical Systems Design.
Proceedings of the Information Processing, Proceedings of IFIP Congress 1971, Volume 2, 1971


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