Akitaka Hiratsuka

According to our database, Akitaka Hiratsuka authored at least 5 papers between 2017 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

IEICE Trans. Electron., 2020

2019

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.

Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera

IEICE Trans. Electron., 2019

A 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.

Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication.

Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017