Akira Yamanaka
According to our database1,
Akira Yamanaka
authored at least 4 papers
between 2003 and 2004.
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Bibliography
2004
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN.
IEEE J. Solid State Circuits, 2004
A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN.
IEEE J. Solid State Circuits, 2003
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LAN.
Proceedings of the ESSCIRC 2003, 2003