Akira Tsuchiya

According to our database, Akira Tsuchiya authored at least 79 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Microelectron. J., 2024

A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS.

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process.

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

IEICE Electron. Express, 2023

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks.

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

IEICE Electron. Express, 2023

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 20th International SoC Design Conference, 2023

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Smart Computational Resource Distribution System with Automatic Classification Interface for CPS.

Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 19th International SoC Design Conference, 2022

Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing.

Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 19th International SoC Design Conference, 2022

A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA.

Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 19th International SoC Design Conference, 2022

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band.

Masataka Inoue, Shinya Nakashioya, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion.

Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

Proceedings of the International Conference on Electronics, Information, and Communication, 2022

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver.

Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems.

Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS.

Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA.

Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2021

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS.

Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the International Conference on Electronics, Information, and Communication, 2021

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers.

Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

IEICE Trans. Electron., 2020

Processing Time Reduction for JPEG Compression Using Pixel Array Conversion.

Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the International SoC Design Conference, 2020

2019

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.

Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera

IEICE Trans. Electron., 2019

A 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier.

Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System.

Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine

Proceedings of the 2019 International SoC Design Conference, 2019

Frequency Discriminator Using a Simple AD Converter for Interface Systems.

Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 2019 International SoC Design Conference, 2019

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS.

Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 2019 International SoC Design Conference, 2019

2018

A 25-Gb/s 13 mW clock and data recovery using C²MOS D-flip-flop in 65-nm CMOS.

Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.

Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion.

Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.

Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication.

Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

FPGA-based transceiver circuit for labeling signal transmission system.

Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the International SoC Design Conference, 2017

Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura

Proceedings of the International SoC Design Conference, 2017

Compact implementation IIR filter in FPGA for noise reduction of sensor signal.

Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the International SoC Design Conference, 2017

2016

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.

Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya

Proceedings of the International SoC Design Conference, 2016

2015

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.

Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage.

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Electron., 2015

Energy reduction by built-in body biasing with single supply voltage operation.

Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.

Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure.

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Electron., 2014

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop.

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation.

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation.

Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Perturbation-immune radiation-hardened PLL with a switchable DMR structure.

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS.

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.

Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera

Proceedings of the International SoC Design Conference, 2011

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS.

Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the International SoC Design Conference, 2011

An area effective forward/reverse body bias generator for within-die variability compensation.

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IPSJ Trans. Syst. LSI Des. Methodol., 2010

A design procedure of predictive RF MOSFET model for compatibility with ITRS.

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Statistical Gate Delay Model for Multiple Input Switching.

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Erect of regularity-enhanced layout on printability and circuit performance of standard cells.

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

High performance on-chip differential signaling using passive compensation for global communication.

Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis.

Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

On-chip high performance signaling using passive compensation.

Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE Trans. Electron., 2007

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

IEICE Trans. Electron., 2007

Worst-case delay analysis considering the variability of transistors and interconnects.

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 2007 International Symposium on Physical Design, 2007

A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.

Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IEICE Trans. Electron., 2006

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.

Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Interconnect RL extraction at a single representative frequency.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Design guideline for resistive termination of on-chip high-speed interconnects.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Return path selection for loop RL extraction.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Performance limitation of on-chip global interconnects for high-speed signaling.

Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Representative Frequency for Interconnect R(f)L(f)C Extraction.

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003