Akira Tamakoshi

According to our database, Akira Tamakoshi authored at least 11 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

IEEE Open J. Circuits Syst., 2021

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE J. Solid State Circuits, 2021

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

2020

High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.

Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2020

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.

Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE J. Solid State Circuits, 2019

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

IEEE Trans. Emerg. Top. Comput., 2017

2016

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.

Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015