Akira Mochizuki
According to our database1,
Akira Mochizuki
authored at least 29 papers
between 1992 and 2017.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Emerg. Top. Comput., 2017
2016
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor.
Proceedings of the IECON 2015, 2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst., 2014
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.
IEICE Trans. Inf. Syst., 2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express, 2014
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.
IEICE Electron. Express, 2014
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
2007
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.
IEICE Trans. Electron., 2007
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
2006
IEICE Trans. Electron., 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
2005
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.
J. Multiple Valued Log. Soft Comput., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
1995
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
1994
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
1992
J. Robotics Mechatronics, 1992