Akira Kotabe

According to our database, Akira Kotabe authored at least 13 papers between 2001 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device.

Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

IEICE Trans. Electron., 2012

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.

Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh

IEICE Trans. Electron., 2012

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura

IEICE Trans. Electron., 2012

A Low-<i>V</i>_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing.

Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh

IEICE Trans. Electron., 2012

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device.

Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing.

Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa

IEEE J. Solid State Circuits, 2011

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

0.5-V Low- V _T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays.

Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi

IEEE J. Solid State Circuits, 2010

2009

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.

Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

IEEE J. Solid State Circuits, 2007

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current.

Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme.

Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

IEEE J. Solid State Circuits, 2005

2001

A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits.

Tadayoshi Enomoto, Akira Kotabe

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001