Akio Furukawa

According to our database, Akio Furukawa authored at least 5 papers between 1983 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2003

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC.

Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami

IEEE J. Solid State Circuits, 2003

1998

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier.

Akira Tanabe, Masaaki Soda, Yasushi Nakahara, Takao Tamura, Kazuyoshi Yoshida, Akio Furukawa

IEEE J. Solid State Circuits, 1998

1996

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology.

Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

IEEE J. Solid State Circuits, 1996

1988

Solving Systems of Algebraic Equations by a General Elimination Method.

Hidetsune Kobayashi, Tetsuro Fujise, Akio Furukawa

J. Symb. Comput., 1988

1983

Multi polynominal remainder sequence and its application to linear diophantine equations.

Akio Furukawa, Tateaki Sasaki

Proceedings of the Computer Algebra, 1983