Akihito Yamamoto
According to our database1,
Akihito Yamamoto
authored at least 2 papers
between 2014 and 2017.
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Bibliography
2017
23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2014
Improving Accuracy of Printed Character Recognition Using Hexagonal Zoning of Directional Histogram Feature.
Proceedings of the 22nd International Conference on Pattern Recognition, 2014