Akihiro Musa

Orcid: 0000-0002-2161-658X

According to our database1, Akihiro Musa authored at least 29 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Modernizing an Operational Real-time Tsunami Simulator to Support Diverse Hardware Platforms.
CoRR, 2024

File I/O Cache Performance of Supercomputer Fugaku Using an Out-of-Core Direct Numerical Simulation Code of Turbulence.
Proceedings of the Computational Science - ICCS 2024, 2024

2023
I/O Performance Evaluation of a Memory-Saving DNS Code on SX-Aurora TSUBASA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2022
A Real-time Flood Inundation Prediction on SX-Aurora TSUBASA.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

Consideration of a Supercomputing System with Cloud Bursting Functionality from an Operational Perspective.
Proceedings of the IEEE International Conference on Cloud Computing Technology and Science, 2022

2020
Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA.
Supercomput. Front. Innov., 2020

Importance of Selecting Data Layouts in the Tsunami Simulation Code.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019
Performance Evaluation of Different Implementation Schemes of an Iterative Flow Solver on Modern Vector Machines.
Supercomput. Front. Innov., 2019

Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA.
Proceedings of the 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing, 2019

Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA.
Proceedings of the Computational Science - ICCS 2019, 2019

2018
Real-time tsunami inundation forecast system for tsunami disaster prevention and mitigation.
J. Supercomput., 2018

Developing Efficient Implementations of Bellman-Ford and Forward-Backward Graph Algorithms for NEC SX-ACE.
Supercomput. Front. Innov., 2018

Performance evaluation of a vector supercomputer SX-aurora TSUBASA.
Proceedings of the International Conference for High Performance Computing, 2018

Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Optimizations of COAWST for a Large Simulation on the Earth Simulator.
Proceedings of the IEEE International Conference on Cluster Computing, 2018

2017
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE.
J. Supercomput., 2017

Performance Evaluation of Quantum ESPRESSO on NEC SX-ACE.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Vectorization-Aware Loop Optimization with User-Defined Code Transformations.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE.
Int. J. Netw. Comput., 2016

2015
A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE.
Proceedings of the Third International Symposium on Computing and Networking, 2015

2011
Effects of 3-D stacked vector cache on energy consumption.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Design and early evaluation of a 3-D die stacked chip multi-vector processor.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Performance evaluation of NEC SX-9 using real science and engineering applications.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Performance tuning and analysis of future vector processors based on the roofline model.
Proceedings of the 10th workshop on MEmory performance, 2009

2008
A shared cache for a chip multi vector processor.
Proceedings of the 9th workshop on MEmory performance, 2008

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

2007
An on-chip cache design for vector processors.
Proceedings of the 2007 workshop on MEmory performance, 2007

2006
Implications of Memory Performance for Highly Efficient Supercomputing of Scientific Applications.
Proceedings of the Parallel and Distributed Processing and Applications, 2006


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