Akihide Sai
Orcid: 0000-0003-0440-1672
According to our database1,
Akihide Sai
authored at least 27 papers
between 2008 and 2022.
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Bibliography
2022
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
2020
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.
IEEE J. Solid State Circuits, 2019
Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019
2018
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.
IEEE J. Solid State Circuits, 2018
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
2014
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".
IEEE J. Solid State Circuits, 2013
2012
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication.
IEEE J. Solid State Circuits, 2012
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2008
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008