Akhilesh Jaiswal

Orcid: 0000-0001-9911-2624

Affiliations:
  • University of Southern California, Los Angeles, CA, USA


According to our database1, Akhilesh Jaiswal authored at least 62 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Energy-Efficient & Real-Time Computer Vision with Intelligent Skipping via Reconfigurable CMOS Image Sensors.
CoRR, 2024

FPCA: Field-Programmable Pixel Convolutional Array for Extreme-Edge Intelligence.
CoRR, 2024

Retina-inspired Object Motion Segmentation.
CoRR, 2024

Hardware-Algorithm Re-engineering of Retinal Circuit for Intelligent Object Motion Segmentation.
CoRR, 2024

Toward High Performance, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ.
CoRR, 2024

A Review on Digital Pixel Sensors.
CoRR, 2024

Sub-Micron Binary HyperPixel Sensor Circuit: In-Pixel Binarization with Variable Thresholding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Hardware-Algorithm Co-Design Enabling Processing-In-Pixel-In-Memory (P<sup>2</sup>M) for Neuromorphic Vision Sensors.
Proceedings of the IEEE International Conference on Acoustics, 2024

Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural Networks: from Algorithms to Technology.
Proceedings of the IEEE International Conference on Acoustics, 2024

A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Toward High-Accuracy, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors.
Frontiers Neuroinformatics, March, 2023

TREBUCHET: Fully Homomorphic Encryption Accelerator for Deep Computation.
IACR Cryptol. ePrint Arch., 2023

Hardware-Algorithm Co-design Enabling Processing-in-Pixel-in-Memory (P2M) for Neuromorphic Vision Sensors.
CoRR, 2023

Object Motion Sensitivity: A Bio-inspired Solution to the Ego-motion Problem for Event-based Cameras.
CoRR, 2023

Cryogenic In-Memory Bit-Serial Addition Using Quantum Anomalous Hall Effect-Based Majority Logic.
IEEE Access, 2023

Enabling ISPless Low-Power Computer Vision.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

Quantum Anomalous Hall Effect-Based Variation Robust Binary Content Addressable Memory.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Design Considerations for 3D Heterogeneous Integration Driven Analog Processing-in-Pixel for Extreme-Edge Intelligence.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

In-Sensor & Neuromorphic Computing Are all You Need for Energy Efficient Computer Vision.
Proceedings of the IEEE International Conference on Acoustics, 2023

A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M).
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Enabling ISP-less Low-Power Computer Vision.
CoRR, 2022

Toward Efficient Hyperspectral Image Processing inside Camera Pixels.
CoRR, 2022

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications.
CoRR, 2022

P<sup>2</sup>M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Variation-aware Design Space Exploration of Mott Memristor-based Neuristors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Modeling the Energy Efficiency of GEMM using Optical Random Access Memory.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

Towards Energy-Efficient Hyperspectral Image Processing Inside Camera Pixels.
Proceedings of the Computer Vision - ECCV 2022 Workshops, 2022

2021
CryoCiM: Cryogenic Compute-in-Memory based on the Quantum Anomalous Hall Effect.
CoRR, 2021

Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications.
CoRR, 2021

Intrinsic Spike Timing Dependent Plasticity in Stochastic Magnetic Tunnel Junctions Mediated by Heat Dynamics.
CoRR, 2021

HYPER-SNN: Towards Energy-efficient Quantized Deep Spiking Neural Networks for Hyperspectral Image Classification.
CoRR, 2021

IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks.
CoRR, 2021

2020
i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs.
IEEE Trans. Circuits Syst., 2020

Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays.
IEEE Trans. Circuits Syst., 2020

In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Array.
CoRR, 2020

2019
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2019

Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy Efficient Neural Computing: A Study of Cross-Layer Approximations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
CoRR, 2018

Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency.
CoRR, 2018

8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing.
CoRR, 2018

2017
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
CoRR, 2017

Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime.
CoRR, 2017

Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets.
CoRR, 2017

Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion.
CoRR, 2017

Image segmentation with stochastic magnetic tunnel junctions and spiking neurons.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction.
CoRR, 2016

Proposal for a Leaky-Integrate-Fire Spiking Neuron based on Magneto-Electric Switching of Ferro-magnets.
CoRR, 2016

MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic.
CoRR, 2016

Spin transfer torque memories for on-chip caches: Prospects and perspectives.
Proceedings of the 17th Latin-American Test Symposium, 2016

Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016


  Loading...