Akhil Reddy Pakala

According to our database, Akhil Reddy Pakala authored at least 5 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator.

Akhil Reddy Pakala, Zhiyu Chen, Kaiyuan Yang

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout.

Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang

IEEE J. Solid State Circuits, January, 2025

2022

MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator.

Dai Li, Akhil Reddy Pakala, Kaiyuan Yang

IEEE Trans. Very Large Scale Integr. Syst., 2022

Reduced Memory Viterbi Decoding for Hardware-accelerated Speech Recognition.

Pani Prithvi Raj, Akhil Reddy Pakala, Nitin Chandrachoodan

ACM Trans. Embed. Comput. Syst., 2022

2021

MePLER: A 20.6-pJ Side-Channel-Aware In-Memory CDT Sampler.

Dai Li, Yan He, Akhil Reddy Pakala, Kaiyuan Yang

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021