Akhil Raj Baranwal

Orcid: 0000-0003-1024-9101

According to our database¹, Akhil Raj Baranwal authored at least 3 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2024

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.

[BibT_eX]

[DOI]

Moazin Khatti

Xingyu Tian

Ahmad Sedigh Baroughi

ACM Trans. Reconfigurable Technol. Syst., September, 2024

2021

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

<i>MemOReL</i>: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Akhil Raj Baranwal

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