Akhil Garg

According to our database, Akhil Garg authored at least 10 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Efficient testing of hierarchical core-based SOCs.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen

Proceedings of the 2014 International Test Conference, 2014

2013

SmartScan - Hierarchical test compression for pin-limited low power designs.

Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj

Proceedings of the 2013 IEEE International Test Conference, 2013

2011

State of the art low capture power methodology.

Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.

Prashant Dubey, Akhil Garg, Shashank Mahajan

J. Electron. Test., 2010

2008

Low Power Test.

Swapnil Bahl, Rajiv Sarkar, Akhil Garg

Proceedings of the 2008 IEEE International Test Conference, 2008

On Chip Jitter Measurement through a High Accuracy TDC.

Akhil Garg, Prashant Dubey

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

GALS Based Shared Test Architecture for Embedded Memories.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Built in Defect Prognosis for Embedded Memories.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.

Akhil Garg, Prashant Dubey

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006