Akhil Garg

Affiliations:
  • Cadence Design Systems, Noida, India
  • STMicroelectronics India, Greater Noida, India (former)


According to our database1, Akhil Garg authored at least 10 papers between 2006 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2014
Efficient testing of hierarchical core-based SOCs.
Proceedings of the 2014 International Test Conference, 2014

2013
SmartScan - Hierarchical test compression for pin-limited low power designs.
Proceedings of the 2013 IEEE International Test Conference, 2013

2011
State of the art low capture power methodology.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.
J. Electron. Test., 2010

2008
Low Power Test.
Proceedings of the 2008 IEEE International Test Conference, 2008

On Chip Jitter Measurement through a High Accuracy TDC.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

GALS Based Shared Test Architecture for Embedded Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Built in Defect Prognosis for Embedded Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006


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