Akash Kumar

Dennis Klar

Mohammad Aasim Ekhtiyar

ACM Trans. Design Autom. Electr. Syst., 2022

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2022

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture.

[BibT_eX]

[DOI]

Mark Wijtvliet

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2022

Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation.

[BibT_eX]

[DOI]

IEEE Micro, 2022

Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems.

[BibT_eX]

[DOI]

Comput., 2022

Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware.

[BibT_eX]

[DOI]

IEEE Access, 2022

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.

[BibT_eX]

[DOI]

Johann Knechtel

Ozgur Sinanoglu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks.

[BibT_eX]

[DOI]

Elias Trommer

Bernd Waschneck

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Securing Hardware through Reconfigurable Nano-Structures.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

ERMES: Efficient Racetrack Memory Emulation System based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

FPGA-Based Database Query Processing on Arbitrarily Wide Tables.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems.

[BibT_eX]

[DOI]

Mohammad Bawatna

Behnaz Ranjbar

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Improving Technology Mapping for And-Inverter-Cones.

[BibT_eX]

[DOI]

Martin Thümmler

Alessandro Tempia Calvino

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Multi-Precision Deep Neural Network Acceleration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

A Versatile Mapping Approach for Technology Mapping and Graph Optimization.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Mark Wijtvliet

ACM Trans. Reconfigurable Technol. Syst., 2021

Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture".

[BibT_eX]

[DOI]

Gopal Raut

IEEE Open J. Circuits Syst., 2021

RECON: Resource-Efficient CORDIC-Based Neuron Architecture.

[BibT_eX]

[DOI]

Gopal Raut

IEEE Open J. Circuits Syst., 2021

Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators.

[BibT_eX]

[DOI]

Tuan Duy Anh Nguyen

IEEE Embed. Syst. Lett., 2021

Toward the Design of Fault-Tolerance- and Peak- Power-Aware Multi-Core Mixed-Criticality Systems.

[BibT_eX]

[DOI]

CoRR, 2021

Compiler Toolchains for Deep Learning Workloads on Embedded Platforms.

[BibT_eX]

[DOI]

Max Sponner

Bernd Waschneck

CoRR, 2021

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies.

[BibT_eX]

[DOI]

Pallab Nath

Ansh Rupani

IEEE Access, 2021

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.

[BibT_eX]

[DOI]

IEEE Access, 2021

Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.

[BibT_eX]

[DOI]

Nishant Gupta

Abhiroop Bhattacharjee

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput.

[BibT_eX]

[DOI]

Abhiroop Bhattacharjee

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference.

[BibT_eX]

[DOI]

Elias Trommer

Bernd Waschneck

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

NMPO: Near-Memory Computing Profiling and Offloading.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.

[BibT_eX]

[DOI]

Mengyun Liu

Anteneh Gebregiorgis

Debjyoti Bhattacharjee

Krishnendu Chakrabarty

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Nano Security: From Nano-Electronics to Secure Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Resource-Efficient Database Query Processing on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Workshop on Data Management on New Hardware, 2021

CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives.

[BibT_eX]

[DOI]

Martin Decky

Samuel Chang Bing Wong

Proceedings of the CODES/ISSS 2021, 2021

Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Improving approximate neural networks for perception tasks through specialized optimization.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2020

Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform.

[BibT_eX]

[DOI]

CoRR, 2020

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics.

[BibT_eX]

[DOI]

CoRR, 2020

FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems.

[BibT_eX]

[DOI]

IEEE Access, 2020

Quantitative Characterization of Reconfigurable Transistor Logic Gates.

[BibT_eX]

[DOI]

IEEE Access, 2020

ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2020

Near Memory Acceleration on High Resolution Radio Astronomy Imaging.

[BibT_eX]

[DOI]

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

A CORDIC Based Configurable Activation Function for ANN Applications.

[BibT_eX]

[DOI]

Gopal Raut

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

SeqL: Secure Scan-Locking for IP Protection.

[BibT_eX]

[DOI]

Seetal Potluri

Aydin Aysu

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Full Approximation of Deep Neural Networks through Efficient Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Introducing FPGA-based Machine Learning on the Edge to Undergraduate Students.

[BibT_eX]

[DOI]

Rajesh C. Panicker

Deepu John

Proceedings of the IEEE Frontiers in Education Conference, 2020

Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

ProxSim: GPU-based Simulation Framework for Cross-Layer Approximate DNN Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

Integr., 2019

Shouji: a fast and efficient pre-alignment filter for sequence alignment.

[BibT_eX]

[DOI]

Bioinform., 2019

Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Design Methodology for Embedded Approximate Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Performance Evaluation of Thermal-Constrained Scheduling Strategies in Multi-core Systems.

[BibT_eX]

[DOI]

Muhammad Usama Sardar

Proceedings of the Computer Performance Engineering - 16th European Workshop, 2019

Exploiting Emerging Reconfigurable Technologies for Secure Devices.

[BibT_eX]

[DOI]

Ansh Rupani

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

High-Throughput BitPacking Compression.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory.

[BibT_eX]

[DOI]

Mahsa Mousavi

Hamid Reza Pourshaghaghi

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

A Hardware/Software Stack for Heterogeneous Systems.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

SLIDER: Fast and Efficient Computation of Banded Sequence Alignment.

[BibT_eX]

[DOI]

CoRR, 2018

Parallel FPGA Router using Sub-Gradient method and Steiner tree.

[BibT_eX]

[DOI]

CoRR, 2018

CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Column Scan Acceleration in Hybrid CPU-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2018

Adaptive Learning and Analytics in Engineering Education.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Teaching, 2018

A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018

Emerging reconfigurable nanotechnologies: can they support future electronics?

[BibT_eX]

[DOI]

Srivatsa Rangachar Srinivasa

Patsy Cadareanu

Xunzhao Yin

Xiaobo Sharon Hu

Pierre-Emmanuel Gaillardon

Vijaykrishnan Narayanan

Proceedings of the International Conference on Computer-Aided Design, 2018

Protecting Communication in Many-Core Systems against Active Attackers.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Reloc - An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles.

[BibT_eX]

[DOI]

Björn Gottschall

Thomas PreuBer

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology mapping flow for emerging reconfigurable silicon nanowire transistors.

[BibT_eX]

[DOI]

Michael Raitza

Bharath Srinivas Prabakaran

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems.

[BibT_eX]

[DOI]

Semeen Rehman

Muhammad Abdullah Hanif

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Column Scan Optimization by Increasing Intra-Instruction Parallelism.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Data Science, 2018

FPGA vs. SIMD: Comparison for Main Memory-Based Fast Column Scan.

[BibT_eX]

[DOI]

Proceedings of the Data Management Technologies and Applications, 2018

Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators.

[BibT_eX]

[DOI]

Bharath Srinivas Prabakaran

Semeen Rehman

Florian Kriebel

Muhammad Abdullah Hanif

Muhammad Shafique

Proceedings of the 55th Annual Design Automation Conference, 2018

SMApproxlib: library of FPGA-based approximate multipliers.

[BibT_eX]

[DOI]

Sanjeev Sripadraj Murthy

Proceedings of the 55th Annual Design Automation Conference, 2018

Lifetime-aware design methodology for dynamic partially reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding.

[BibT_eX]

[DOI]

Bharath Srinivas Prabakaran

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Exploiting transistor-level reconfiguration to optimize combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding.

[BibT_eX]

[DOI]

Walaa El-Harouni

Semeen Rehman

Rehan Hafiz

Muhammad Shafique

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accounting for systematic errors in approximate computing.

[BibT_eX]

[DOI]

Martin Bruestel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Locality-Aware CTA Clustering for Modern GPUs.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Leakage aware resource management approach with machine learning optimization framework for partially reconfigurable architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms.

[BibT_eX]

[DOI]

Pham Nam Khanh

Khin Mi Mi Aung

Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Automatic framework to generate reconfigurable accelerators for option pricing applications.

[BibT_eX]

[DOI]

Pham Nam Khanh

Khin Mi Mi Aung

Daniel G. Chavarría-Miranda

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

X: A Comprehensive Analytic Model for Parallel Machines.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

SFU-Driven Transparent Approximation Acceleration on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Supercomputing, 2016

Architectural-space exploration of approximate multipliers.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

XNoC: A non-intrusive TDM circuit-switched Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Cross-layer fault-tolerant design of real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A flexible inexact TMR technique for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults.

[BibT_eX]

[DOI]

Daniel G. Chavarría-Miranda

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Critical points based register-concurrency autotuning for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Autonomous Soft-Error Tolerance of FPGA Configuration Bits.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Nano-satellite swarm for SAR applications: design and robust scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., 2015

Correlation ratio based volume image registration on GPUs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Adaptive and transparent cache bypassing for GPUs.

[BibT_eX]

[DOI]

Gert-Jan van den Braak

Proceedings of the International Conference for High Performance Computing, 2015

Hardware task migration module for improved fault tolerance and predictability.

[BibT_eX]

[DOI]

Jasper Kuijsten

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Generic scrubbing-based architecture for custom error correction algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Fine-Grained Synchronizations and Dataflow Programming on GPUs.

[BibT_eX]

[DOI]

Gert-Jan van den Braak

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Transit: A Visual Analytical Model for Multithreaded Machines.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing, 2015

An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

ParaLaR: A parallel FPGA router based on Lagrangian relaxation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Designing inexact systems efficiently using elimination heuristics.

[BibT_eX]

[DOI]

Jeremy Schlachter

Christian C. Enz

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamic reconfigurable puncturing for secure wireless communication.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

(AS)2: accelerator synthesis using algorithmic skeletons for rapid design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Qingsong Wei

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Energy-aware task mapping and scheduling for reliable embedded computing systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Communication and migration energy aware task mapping for reliable multiprocessor systems.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2014

A multi-stage thermal management strategy for 3D multicores.

[BibT_eX]

[DOI]

Dipika Suresh

Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Lightweight Bare-Metal Stateful Firewall.

[BibT_eX]

[DOI]

Yihuan Xing

Ford-Long Wong

Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

A heterogeneous platform with GPU and FPGA for power efficient high performance computing.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Design and robust scheduling of nano-satellite swarm for synthetic aperture radar applications.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

A multi-stage leakage aware resource management technique for reconfigurable architectures.

[BibT_eX]

[DOI]

Pham Nam Khanh

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

FPGA-based high throughput XTS-AES encryption/decryption for storage area network.

[BibT_eX]

[DOI]

Yi Wang

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Multi-directional error correction schemes for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Sidharth Maheshwari

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Criticality-aware scrubbing mechanism for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Project-Based Learning in Embedded Systems Education Using an FPGA Platform.

[BibT_eX]

[DOI]

Rajesh Chandrasekhara Panicker

Shakith Fernando

IEEE Trans. Educ., 2013

Computational analysis of xanthine dehydrogenase enzyme from different source organisms.

[BibT_eX]

[DOI]

Netw. Model. Anal. Health Informatics Bioinform., 2013

CADSE: communication aware design space exploration for efficient run-time MPSoC management.

[BibT_eX]

[DOI]

Jigang Wu

Frontiers Comput. Sci., 2013

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Real-time and low power embedded ℓ1-optimization solver design.

[BibT_eX]

[DOI]

Zhi Ping Ang

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

High Speed Video Processing Using Fine-Grained Processing on FPGA Platform.

[BibT_eX]

[DOI]

Zhi Ping Ang

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

RAPIDITAS: RAPId Design-Space-Exploration Incorporating Trace-Based Analysis and Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Run-time mapping for reliable many-cores based on energy/performance trade-offs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Communication and migration energy aware design space exploration for multicore systems with intermittent faults.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Mapping on multi/many-core systems: survey of current and emerging trends.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2013

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Review of polynomia and related realms by Dan Kalman.

[BibT_eX]

[DOI]

SIGACT News, 2012

A design flow for partially reconfigurable heterogeneous multi-processor platforms.

[BibT_eX]

[DOI]

Jiashu Li

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Fault-aware task re-mapping for throughput constrained multimedia applications on NoC-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Energy-Aware Communication and Remapping of Tasks for Reliable Multimedia Multiprocessor Systems.

[BibT_eX]

[DOI]

Rajesh Chandrasekhara Panicker

Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Development of an FPGA-based real-time P300 speller.

[BibT_eX]

[DOI]

Kanav Khurana

Pooja Gupta

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Acceleration of distance-to-default with hardware-software co-design.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management.

[BibT_eX]

[DOI]

Wu Jigang

Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

A Design Space Exploration Methodology for Application Specific MPSoC Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Bringing soccer to the field of real-time embedded systems education.

[BibT_eX]

[DOI]

Shakith Fernando

Manmohan Manoharan

Proceedings of the 6th Workshop on Embedded Systems Education, 2011

An Automated Flow to Map Throughput Constrained Applications to a MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011

An MPSoC design approach for multiple use-cases of throughput constrainted applications.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Compilers, 2011

2010

Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Run-time mapping of multiple communicating tasks on MPSoC platforms.

[BibT_eX]

[DOI]

Wu Jigang

Proceedings of the International Conference on Computational Science, 2010

Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms.

[BibT_eX]

[DOI]

Wu Jigang

J. Syst. Archit., 2010

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee.

[BibT_eX]

[DOI]

Zhiyao Joseph Yang

Proceedings of the International Conference on Field-Programmable Technology, 2010

Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

A predictable communication assist.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Performance evaluation of concurrently executing parallel applications on multi-processor systems.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Analyzing composability of applications on MPSoC platforms.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Enabling MPSoC Design Space Exploration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Wireless Networks, 2008

Vectorization of Reed Solomon Decoding and Mapping on the EVP.

[BibT_eX]

[DOI]

Kees van Berkel

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Global Analysis of Resource Arbitration for MPSoC.

[BibT_eX]

[DOI]

Bart Mesman

Jef L. van Meerbergen

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Efficient techniques for improved QoS performance in WDM optical burst switched networks.

[BibT_eX]

[DOI]

Gurusamy Mohan

M. Ashish

Comput. Commun., 2005

2002

Membrane Systems and Distributed Computing.

[BibT_eX]

[DOI]

Gabriel Ciobanu

Rahul Desai