Ajoy Mandal

Orcid: 0000-0002-6455-4526

According to our database1, Ajoy Mandal authored at least 10 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

2023
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023

2021
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Determination of Fat, SNF and Protein Content in Cow Milk from the Voltage Output of 'MilkTester'.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021

2020
Optimal Choice of Waveform for Library Characterization for Accurate Delay Calculation.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2018
Live Demonstration: Low Power Consuming Organic Field-Effect Transistors Based Flexible Temperature Sensor for Medical Applications.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2011
DFM: Impact analysis in a high performance design.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2009
Optimization strategies to improve statistical timing.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2004
An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004


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