Ajith Sivadasan

According to our database, Ajith Sivadasan authored at least 6 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI.

Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Workload dependent reliability timing analysis flow.

Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results.

Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Activity profiling: Review of different solutions to develop reliable and performant design.

Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis.

Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel

Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Study of workload impact on BTI HCI induced aging of digital circuits.

Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016