Ajith Amerasekera

According to our database, Ajith Amerasekera authored at least 13 papers between 1993 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links.

Hyeon-Min Bae, Ajith Amerasekera

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee.

Gerrit den Besten, Ajith Amerasekera

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems.

Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2014

ES2: Data centers to support tomorrow's cloud.

Leland Chang, Ajith Amerasekera, Takashi Hashimoto

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems.

Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

ES3: High-speed communications on 4 wheels: What's in your next car?

Nicola Da Dalt, Ajith Amerasekera

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

Foreword.

Ajith Amerasekera, Makoto Nagata

Proceedings of the Symposium on VLSI Circuits, 2012

2010

Ultra low power electronics in the next decade.

Ajith Amerasekera

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2008

The Changing Design Landscape.

Ajith Amerasekera

IEEE Des. Test Comput., 2008

2007

Concurrent Optimization of Technology and Design for Nano CMOS.

Ajith Amerasekera

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002

A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.

Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1993

ESD: a pervasive reliability concern for IC technologies.

Charvaka Duvvury, Ajith Amerasekera

Proc. IEEE, 1993