Ajit Pal

According to our database1, Ajit Pal authored at least 50 papers between 1986 and 2016.

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Bibliography

2016
Extending light-trail into elastic optical networks for dynamic traffic grooming.
Opt. Switch. Netw., 2016

2015
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence.
J. Low Power Electron., 2015

Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating.
J. Low Power Electron., 2015

A load balanced approach of multicast routing and wavelength assignment in WDM networks.
Int. J. Commun. Networks Distributed Syst., 2015

2014
Loop unrolling with fine grained power gating for runtime leakage power reduction.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013
Formal Verification of Architectural Power Intent.
IEEE Trans. Very Large Scale Integr. Syst., 2013

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis.
J. Low Power Electron., 2013

A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture
CoRR, 2013

Formal Verification of Hardware / Software Power Management Strategies.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations.
LAP Lambert Academic Publishing, ISBN: 978-3-659-27391-9, 2013

2012
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques.
J. Low Power Electron., 2012

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework.
Proceedings of the International Symposium on Electronic System Design, 2012

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture.
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012

2011
Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks.
Photonic Netw. Commun., 2011

Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy.
Proceedings of the Distributed Computing and Networking - 12th International Conference, 2011

2010
Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning.
Photonic Netw. Commun., 2010

A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation.
J. Low Power Electron., 2010

Traffic grooming in WDM mesh networks using dynamic path selection strategy.
Proceedings of the 7th International Conference on Wireless and Optical Communications Networks, 2010

Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm.
Proceedings of the Distributed Computing and Networking, 11th International Conference, 2010

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
Proceedings of the 47th Design Automation Conference, 2010

2009
Synthesis & Testing for Low Power.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
A power-aware wireless sensor network based bridge monitoring system.
Proceedings of the 16th International Conference on Networks, 2008

A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks.
Proceedings of the 16th International Conference on Networks, 2008

A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning.
Proceedings of the Distributed Computing and Networking, 9th International Conference, 2008

Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Low Power Sensor Node for a Wireless Sensor Network.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
On finding the minimum test set of a BDD-based circuit.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004
Synthesis of Low Power High Performance Dual-VT PTL Circuits.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks.
Proceedings of the Distributed Computing, 2004

2003
Synthesis of Dual-VT Dynamic CMOS Circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Synthesis of high performance low power PTL circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Synthesis of High Performance Low Power Dynamic CMOS Circuits.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

1999
Deadline Assignment in Multiprocessor-Based Fault-Tolerant Systems.
Proceedings of the High Performance Computing, 1999

1998
DDSCHED: A distributed dynamic real-time scheduling algorithm.
Parallel Distributed Comput. Pract., 1998

An algorithm for finding a non-trivial lower bound for channel routing1.
Integr., 1998

1997
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
A layered architecture for real-time systems.
Microprocess. Microsystems, 1996

1995
Computing area and wire length efficient routes for channels.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A general graph theoretic framework for multi-layer channel routing.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1993
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1986
An Algorithm for Optimal Logic Design Using Multiplexers.
IEEE Trans. Computers, 1986


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