Ajeya Naithani

Orcid: 0000-0002-8291-4230

According to our database1, Ajeya Naithani authored at least 11 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains.
IEEE Micro, 2024

2023
Decoupled Vector Runahead.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors.
IEEE Trans. Computers, 2022

The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture.
ACM Trans. Archit. Code Optim., 2022

Vector Runahead for Indirect Memory Accesses.
IEEE Micro, 2022

Reliability-Aware Runahead.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Vector Runahead.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
The Forward Slice Core Microarchitecture.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Precise Runahead Execution.
IEEE Comput. Archit. Lett., 2019

2018
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors.
IEEE Trans. Computers, 2018

2017
Reliability-Aware Scheduling on Heterogeneous Multicore Processors.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017


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