Ajay Kumar Verma

According to our database, Ajay Kumar Verma authored at least 29 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Deep learning based network similarity for model selection.

Kushal Veer Singh, Ajay Kumar Verma, Lovekesh Vig

Data Sci., 2021

2012

Document image binarization using wavelets for OCR applications.

C. Patvardhan, Ajay Kumar Verma, C. Vasantha Lakshmi

Proceedings of the Eighth Indian Conference on Vision, Graphics and Image Processing, 2012

2010

Pre-Synthesis Optimization of Arithmetic Circuits.

Ajay Kumar Verma

PhD thesis, 2010

Improving FPGA Performance for Carry-Save Arithmetic.

Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne

IEEE Trans. Very Large Scale Integr. Syst., 2010

Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.

Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Generating Distributed Query Processing Plans Using Genetic Algorithm.

T. V. Vijay Kumar, Vikram Singh, Ajay Kumar Verma

Proceedings of the International Conference on Data Storage and Data Engineering, 2010

2009

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne

ACM Trans. Reconfigurable Technol. Syst., 2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne

Des. Autom. Embed. Syst., 2009

Arithmetic optimization for custom instruction set synthesis.

Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne

Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Iterative layering: Optimizing arithmetic circuits by structuring the information flow.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Hybrid LZA: a near optimal implementation of the leading zero anticipator.

Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Challenges in Automatic Optimization of Arithmetic Circuits.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008

Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the Design, Automation and Test in Europe, 2008

Fast, quasi-optimal, and pipelined instruction-set extensions.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automatic synthesis of compressor trees: reevaluating large counters.

Ajay Kumar Verma, Paolo Ienne

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 44th Design Automation Conference, 2007

Enhancing FPGA Performance for Arithmetic Circuits.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar

Proceedings of the 44th Design Automation Conference, 2007

Rethinking custom ISE identification: a new processor-agnostic method.

Ajay Kumar Verma, Philip Brisk, Paolo Ienne

Proceedings of the 2007 International Conference on Compilers, 2007

An optimistic and conservative register assignment heuristic for chordal graphs.

Philip Brisk, Ajay Kumar Verma, Paolo Ienne

Proceedings of the 2007 International Conference on Compilers, 2007

Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.

Ajay Kumar Verma, Paolo Ienne

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.

Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Towards the automatic exploration of arithmetic-circuit architectures.

Ajay Kumar Verma, Paolo Ienne

Proceedings of the 43rd Design Automation Conference, 2006

2004

Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.

Ajay Kumar Verma, Paolo Ienne

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Arithmetic Transformations to Maximise the Use of Compressor Trees.

Paolo Ienne, Ajay Kumar Verma

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004