Ajay Khoche

According to our database1, Ajay Khoche authored at least 24 papers between 1992 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System.
IEEE Des. Test, 2013

2010
STIL P1450.4: A standard for test flow specification.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
STDF Memory Fail Datalog Standard.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
A Tutorial on STDF Fail Datalog Standard.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges.
IEEE Des. Test Comput., 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics.
Proceedings of the 2006 IEEE International Test Conference, 2006

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format.
Proceedings of the 15th Asian Test Symposium, 2006

2003
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits.
J. Electron. Test., 2003

2002
Test Economics for Multi-site Test with Modern Cost Reduction Techniques.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Vector Compression Using EDA-ATE Synergies.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Packet-Based Input Test Data Compression Techniques.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Tackling test trade-offs from design, manufacturing to market using economic modeling.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A new methodology for improved tester utilization.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1997
Critical hazard free test generation for asynchronous circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

ACT: A DFT Tool for Self-Timed Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995
A partial scan methodology for testing self-timed circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

DFT for fast testing of self-timed control circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Testing self-timed circuits using partial scan.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994
Testing micropipelines.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1992
A Behavioral Fault Simulator for Ideal.
IEEE Des. Test Comput., 1992

A Behavioral Fault Simulator For Ideal.
Proceedings of the Fifth International Conference on VLSI Design, 1992


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