Ajai Jain

According to our database, Ajai Jain authored at least 11 papers between 1995 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

An approach for optimisation of flexible flow shop group scheduling with sequence dependent set-up time and preventive maintenance.

Ajai Jain, Avichal Jain

Int. J. Comput. Aided Eng. Technol., 2022

2020

An integrated approach for multi-period manufacturing planning of job-shops.

Viraj Tyagi, Ajai Jain, P. K. Jain

Int. J. Manuf. Res., 2020

2016

New setup-oriented dispatching rules for a stochastic dynamic job shop manufacturing system with sequence-dependent setup times.

Pankaj Sharma, Ajai Jain

Concurr. Eng. Res. Appl., 2016

2013

An approach for integration of process planning and scheduling.

Rakesh Kumar Phanden, Ajai Jain, Rajiv Verma

Int. J. Comput. Integr. Manuf., 2013

2012

Experimental Investigation of Machining Characteristics for the WEDM of Al/ZrO2(p)-PRMMC.

Sanjeev Kumar Garg, Alakesh Manna, Ajai Jain

Int. J. Manuf. Mater. Mech. Eng., 2012

2011

Integration of process planning and scheduling: a state-of-the-art review.

Rakesh Kumar Phanden, Ajai Jain, Rajiv Verma

Int. J. Comput. Integr. Manuf., 2011

2003

Stochastic Image Compression Using Fractals.

Aditya Kapoor, Kush Arora, Ajai Jain, G. P. Kapoor

Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003

1998

Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms.

V. Rajesh, Ajai Jain

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit.

Amey Karkare, Manoj Singla, Ajai Jain

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1996

An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits.

Dhruva R. Chakrabarti, Ajai Jain

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.

Dhruva R. Chakrabarti, Ajai Jain

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995