Aiqun Cao

According to our database, Aiqun Cao authored at least 12 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era.

Aiqun Cao

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2012

Clock mesh framework.

Pinaki Chakrabarti, Vikram Bhatt, Dwight D. Hill, Aiqun Cao

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2007

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.

Ruibing Lu, Aiqun Cao, Cheng-Kok Koh

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Postlayout optimization for synthesis of Domino circuits.

Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh

ACM Trans. Design Autom. Electr. Syst., 2006

2005

Synthesis of skewed logic circuits.

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy

ACM Trans. Design Autom. Electr. Syst., 2005

Improving the scalability of SAMBA bus architecture.

Ruibing Lu, Aiqun Cao, Cheng-Kok Koh

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Post-layout logic duplication for synthesis of domino circuits with complex gates.

Aiqun Cao, Ruibing Lu, Cheng-Kok Koh

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Post-layout logic optimization of domino circuits.

Aiqun Cao, Cheng-Kok Koh

Proceedings of the 41th Design Automation Conference, 2004

2003

Non-Crossing OBDDs for Mapping to Regular Circuit Structures.

Aiqun Cao, Cheng-Kok Koh

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Integer linear programming-based synthesis of skewed logic circuits.

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Synthesis of Selectively Clocked Skewed Logic Circuits.

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.

Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001