Aiman H. El-Maleh

According to our database, Aiman H. El-Maleh authored at least 63 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Accelerating memory and I/O intensive HPC applications using hardware compression.

Saleh Alsaleh, Muhammad E. S. Elrabaa, Aiman El-Maleh, Khaled A. Daud, Ayman Hroub, Muhamed F. Mudawar, Thierry Tonellot

J. Parallel Distributed Comput., 2024

2023

Optimization of FPGA-based CNN accelerators using metaheuristics.

Sadiq M. Sait, Aiman El-Maleh, Mohammad Altakrouri, Ahmad Shawahna

J. Supercomput., March, 2023

2022

DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm.

Mahmoud Habboush, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Saleh Alsaleh

Microprocess. Microsystems, April, 2022

FxP-QNet: A Post-Training Quantizer for the Design of Mixed Low-Precision DNNs With Dynamic Fixed-Point Representation.

Ahmad Shawahna, Sadiq M. Sait, Aiman El-Maleh, Irfan Ahmad

IEEE Access, 2022

2021

Time redundancy and gate sizing soft error-tolerant based adder design.

Aiman H. El-Maleh, Ghashmi H. Bin Talib

Integr., 2021

2019

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review.

Ahmad Shawahna, Sadiq M. Sait, Aiman El-Maleh

IEEE Access, 2019

2018

Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits.

Ahmad T. Sheikh, Aiman H. El-Maleh

J. Circuits Syst. Comput., 2018

2017

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.

Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait

IEEE Trans. Very Large Scale Integr. Syst., 2017

An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing.

Ahmad T. Sheikh, Aiman H. El-Maleh

Integr., 2017

A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization.

Aiman H. El-Maleh

Integr., 2017

Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits.

Aiman H. El-Maleh

IET Comput. Digit. Tech., 2017

2016

A low-cost platform for the prototyping and characterization of digital circuit IPs.

Muhammad E. S. Elrabaa, Amran Al-Aghbari, Mohammed Alasli, Aiman El-Maleh, Abdelhafid Bouhraoua, Mohammad R. Alshayeb

Integr., 2016

Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits.

Aiman H. El-Maleh

IET Comput. Digit. Tech., 2016

Cuckoo search based resource optimization of datacenters.

Sadiq M. Sait, Abubakar Bala, Aiman H. El-Maleh

Appl. Intell., 2016

2015

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits.

Aiman H. El-Maleh, Khaled A. Daud

IEEE Trans. Reliab., 2015

Towards a Test Definition Language for Integrated Circuits.

Mohammad R. Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari, Aiman H. El-Maleh, Abdelhafid Bouhraoua

J. Circuits Syst. Comput., 2015

State assignment for area minimization of sequential circuits based on cuckoo search optimization.

Aiman H. El-Maleh, Sadiq M. Sait, Abubakar Bala

Comput. Electr. Eng., 2015

State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm.

Aiman H. El-Maleh

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015

A sequential circuit fault tolerance technique with enhanced area and power.

Aiman H. El-Maleh

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015

2014

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits.

Aiman H. El-Maleh, Feras Chikh Oughali

Microelectron. Reliab., 2014

A finite state machine based fault tolerance technique for sequential circuits.

Aiman H. El-Maleh, Ayed S. Al-Qahtani

Microelectron. Reliab., 2014

2013

Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits.

Aiman H. El-Maleh, Ahmad T. Sheikh, Sadiq M. Sait

Appl. Soft Comput., 2013

Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme.

Aiman H. El-Maleh, Feras Chikh Oughali

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012

A new scheme of test data compression based on equal-run-length coding (ERLC).

Wenfa Zhan, Aiman El-Maleh

Integr., 2012

2011

Test data compression based on geometric shapes.

Aiman El-Maleh, Saif al Zahir, Esam Khan

Comput. Electr. Eng., 2011

2010

A scheme of test data compression based on coding of even bits marking and selective output inversion.

Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh

Comput. Electr. Eng., 2010

2009

Defect-tolerant n²-transistor structure for reliable nanoelectronic designs.

Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan

IET Comput. Digit. Tech., 2009

Reconfigurable broadcast scan compression using relaxation-based test vector decomposition.

Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani

IET Comput. Digit. Tech., 2009

A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC).

Wenfa Zhan, Aiman El-Maleh

Proceedings of the 13th International Conference on Computers Supported Cooperative Work in Design, 2009

2008

Efficient test compression technique based on block merging.

Aiman H. El-Maleh

IET Comput. Digit. Tech., 2008

Test data compression for system-on-a-chip using extended frequency-directed run-length code.

Aiman H. El-Maleh

IET Comput. Digit. Tech., 2008

New Technique for Improving Performance of LDPC Codes in the Presence of Trapping Sets.

Esa Alghonaim, Aiman El-Maleh, Mohamed Adnan Landolsi

EURASIP J. Wirel. Commun. Netw., 2008

Transistor-level based defect tolerance for reliable nanoelectronics.

Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki

Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

Using input/output queues to increase LDPC decoder performance.

Esa Alghonaim, Aiman El-Maleh, Mohamed Adnan Landolsi

Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007

Efficient test compaction for combinational circuits based on Fault detection count-directed clustering.

Aiman El-Maleh, S. Saqib Khursheed

IET Comput. Digit. Tech., 2007

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos.

Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani

Proceedings of the 16th Asian Test Symposium, 2007

2006

Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.

Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Evolutionary algorithms for VLSI multi-objective netlist partitioning.

Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji

Eng. Appl. Artif. Intell., 2006

Finite state machine state assignment for area and power minimization.

Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An efficient test vector compression technique based on block merging.

Aiman El-Maleh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

An efficient test relaxation technique for synchronous sequential circuits.

Aiman H. El-Maleh, Khaled Al-Utaibi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Test vector decomposition-based static compaction algorithms for combinational circuits.

Aiman H. El-Maleh, Yahya E. Osais

ACM Trans. Design Autom. Electr. Syst., 2003

General iterative heuristics for VLSI multiobjective partitioning.

Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning.

Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

On efficient extraction of partially specified test sets for synchronous sequential circuits.

Aiman H. El-Maleh, Khaled Al-Utaibi

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Enhancing performance of iterative heuristics for VLSI netlist partitioning.

Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A static test compaction technique for combinational circuits based on independent fault clustering.

Yahya E. Osais, Aiman H. El-Maleh

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A hybrid test compression technique for efficient testing of systems-on-a-chip.

Aiman H. El-Maleh

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002

An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits.

Aiman El-Maleh, Ali Al-Suwaiyan

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

An efficient test relaxation technique for combinational circuits based on critical path tracing.

Aiman El-Maleh, Ali Al-Suwaiyan

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression.

Aiman H. El-Maleh, Raslan H. Al-Abaji

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip.

Aiman El-Maleh, Esam Khan, Saif al Zahir

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A retiming-based test pattern generator design for built-in self test of data path architectures.

Aiman H. El-Maleh, Yahya E. Osais

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An efficient test vector compression technique based on geometric shapes [system-on-a-chip].

Saif al Zahir, Aiman El-Maleh, Esam Khan

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement.

Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1998

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.

Aiman H. El-Maleh, Mark Kassab, Janusz Rajski

Proceedings of the 35th Conference on Design Automation, 1998

1997

Behavior and testability preservation under the retiming transformation.

Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996

A complexity analysis of sequential ATPG.

Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Delay-fault testability preservation of the concurrent decomposition and factorization transformations.

Aiman H. El-Maleh, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Testability Implications of Performance-Driven Logic Synthesis.

Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly

IEEE Des. Test Comput., 1995

Complexity of sequential ATPG.

Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski

Proceedings of the 1995 European Design and Test Conference, 1995

On Test Set Preservation of Retimed Circuits.

Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly

Proceedings of the 32st Conference on Design Automation, 1995

1992

Recent advances in logic synthesis with testability.

Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992