Aida Varzaghani

According to our database, Aida Varzaghani authored at least 8 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2016

A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.

Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2013

A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications.

Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos

IEEE J. Solid State Circuits, 2013

A 10.3GS/s 6b flash ADC for 10G Ethernet applications.

Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2009

A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization.

Aida Varzaghani, Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2009

2007

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.

Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman

IEEE J. Solid State Circuits, 2007

2006

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter.

Aida Varzaghani, Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2006

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration.

Aida Varzaghani, Chih-Kong Ken Yang

IEEE J. Solid State Circuits, 2006