Aibin Yan

Orcid: 0000-0003-0024-987X

According to our database1, Aibin Yan authored at least 98 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization.
IEEE Trans. Aerosp. Electron. Syst., August, 2024

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.
J. Circuits Syst. Comput., March, 2024

A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements.
J. Electron. Test., February, 2024

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Efficient design approaches to CMOS full adder circuits.
Microelectron. J., 2024

SRBML: A Single-Event-Upset Recoverable and BTI-Mitigated Latch Design for Long-Term Reliability Enhancement.
Proceedings of the IEEE International Test Conference in Asia, 2024

SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications.
Proceedings of the IEEE International Test Conference in Asia, 2024

A RO-Integrated-LFSR-Based Nonlinear Strong PUF with Intrinsic Modeling Attacks Resilience.
Proceedings of the IEEE International Test Conference in Asia, 2024

Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.
IEEE Trans. Aerosp. Electron. Syst., December, 2023

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications.
Microelectron. J., September, 2023

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications.
IEEE Des. Test, August, 2023

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.
J. Electron. Test., June, 2023

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications.
IEEE Trans. Emerg. Top. Comput., 2023

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness.
Proceedings of the IEEE International Test Conference in Asia, 2023

A Low Overhead and Double-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of Low-Cost Approximate CMOS Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.
Proceedings of the IEEE European Test Symposium, 2023

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery.
Proceedings of the 10th International Conference on Dependable Systems and Their Applications, 2023

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A High-Performance and P-Type FeFET-Based Non-Volatile Latch.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.
IEEE Trans. Emerg. Top. Comput., 2022

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications.
IEEE Trans. Aerosp. Electron. Syst., 2022

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Integr., 2022

Machine learning classification algorithm for VLSI test cost reduction.
Integr., 2022

Evaluation and Test of Production Defects in Hardened Latches.
IEICE Trans. Inf. Syst., 2022

Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement.
IEEE Des. Test, 2022

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.
Proceedings of the IEEE International Test Conference in Asia, 2022

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
IEEE Trans. Emerg. Top. Comput., 2021

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.
IEEE Trans. Emerg. Top. Comput., 2021

Intra Coding With Geometric Information for Urban Building Scenes.
IEEE Trans. Circuits Syst. Video Technol., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.
Microelectron. J., 2021

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.
J. Electron. Test., 2021

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing.
Proceedings of the IEEE International Test Conference in Asia, 2021

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets.
Proceedings of the 8th International Conference on Dependable Systems and Their Applications, 2021

2020
Architecture of Cobweb-Based Redundant TSV for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets.
IEEE Trans. Circuits Syst., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.
IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.
IEEE Trans. Computers, 2020

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.
IEEE Access, 2020

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout.
IEEE Trans. Reliab., 2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets.
IEEE Access, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.
Proceedings of the IEEE International Test Conference in Asia, 2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
Proceedings of the 24th IEEE European Test Symposium, 2019

Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors.
Proceedings of the 6th International Conference on Dependable Systems and Their Applications, 2019

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
T2FA: Transparent Two-Factor Authentication.
IEEE Access, 2018

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.
Proceedings of the IEEE International Test Conference in Asia, 2018

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.
Microelectron. J., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.
IEICE Trans. Electron., 2017

A transient pulse dually filterable and online self-recoverable latch.
IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.
IEICE Electron. Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.
Microelectron. Reliab., 2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.
IEICE Trans. Electron., 2015

2014
Design of a Radiation Hardened Latch for Low-Power Circuits.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014


  Loading...