Ai He
Orcid: 0000-0002-1703-0076
According to our database1,
Ai He
authored at least 10 papers
between 2013 and 2024.
Collaborative distances:
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Bibliography
2024
A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology.
Microelectron. J., 2024
2023
2021
Microelectron. J., 2021
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology.
Microelectron. J., 2021
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2015
Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015
2013
Proceedings of TextGraphs@EMNLP 2013: the 8th Workshop on Graph-based Methods for Natural Language Processing, 2013