Ahsen Ejaz

According to our database, Ahsen Ejaz authored at least 7 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling.

Panagiotis Strikos, Ahsen Ejaz, Ioannis Sourdis

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

2023

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

FastTrackNoC: A NoC with FastTrack Router Datapaths.

Ahsen Ejaz, Ioannis Sourdis

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers.

Ahsen Ejaz, Vassilis Papaefstathiou, Ioannis Sourdis

IEEE/ACM Trans. Netw., 2021

2018

DDRNoC: Dual Data-Rate Network-on-Chip.

Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis

ACM Trans. Archit. Code Optim., 2018

FreewayNoC: A DDR NoC with Pipeline Bypassing.

Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

2013

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip.

Ahsen Ejaz, Axel Jantsch

Proceedings of the Network on Chip Architectures, 2013