Ahmet Can Mert

Orcid: 0000-0002-7400-2450

Affiliations:
  • Graz University of Technology, Austria


According to our database1, Ahmet Can Mert authored at least 43 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Proteus: A Pipelined NTT Architecture Generator.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024

ModHE: Modular Homomorphic Encryption Using Module Lattices Potentials and Limitations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

OpenNTT: An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE.
IACR Cryptol. ePrint Arch., 2024

Exploring the Advantages and Challenges of Fermat NTT in FHE Acceleration.
IACR Cryptol. ePrint Arch., 2024

Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024

2023
A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange.
IEEE Trans. Computers, June, 2023

KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Medha: Microcoded Hardware Accelerator for computing on Encrypted Data.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

Parallel Hardware for Isogeny-based VDF: Attacker's Perspective.
IACR Cryptol. ePrint Arch., 2023

A Hardware Implementation of MAYO Signature Scheme.
IACR Cryptol. ePrint Arch., 2023

PROTEUS: A Tool to generate pipelined Number Theoretic Transform Architectures for FHE and ZKP applications.
IACR Cryptol. ePrint Arch., 2023

REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A Survey of Software Implementations for the Number Theoretic Transform.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

2022
CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication.
Microprocess. Microsystems, March, 2022

Efficient number theoretic transform implementation on GPU for homomorphic encryption.
J. Supercomput., 2022

Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Evaluation.
IEEE Trans. Computers, 2022

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform.
IEEE Trans. Computers, 2022

Exploring RNS for Isogeny-based Cryptography.
IACR Cryptol. ePrint Arch., 2022

Small MACs from Small Permutations.
IACR Cryptol. ePrint Arch., 2022

KaLi: A Crystal for Post-Quantum Security.
IACR Cryptol. ePrint Arch., 2022

An Accelerated GPU Library for Homomorphic Encryption Operations of BFV Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme.
IACR Cryptol. ePrint Arch., 2021

Accelerator for Computing on Encrypted Data.
IACR Cryptol. ePrint Arch., 2021

2020
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2020

FPGA implementation of a run-time configurable NTT-based polynomial multiplication hardware.
Microprocess. Microsystems, 2020

Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Applications.
IACR Cryptol. ePrint Arch., 2020

A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier Architecture.
IACR Cryptol. ePrint Arch., 2019

Novel Approximate Absolute Difference Hardware.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
An HEVC fractional interpolation hardware using memory based constant multiplication.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

An efficient FPGA implementation of HEVC intra prediction.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Reconfigurable Fractional Interpolation Hardware for VVC Motion Compensation.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Low Power Versatile Video Coding (VVC) Fractional Interpolation Hardware.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

2017
High performance 2D transform hardware for future video coding.
IEEE Trans. Consumer Electron., 2017

Reconfigurable intra prediction hardware for future video coding.
IEEE Trans. Consumer Electron., 2017

An FPGA implementation of future video coding 2D transform.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

Pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

2016
A computation and energy reduction technique for HEVC Discrete Cosine Transform.
IEEE Trans. Consumer Electron., 2016

Low complexity HEVC sub-pixel motion estimation technique and its hardware implementation.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016


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