Ahmed M. Shams

According to our database, Ahmed M. Shams authored at least 10 papers between 1998 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

NEDA: a low-power high-performance DCT architecture.

Ahmed M. Shams, Archana Chidanandan, Wendi Pan, Magdy A. Bayoumi

IEEE Trans. Signal Process., 2006

2004

Low Power Full Search Block Matching Motion Estimation Vlsi Architectures.

Mohamed A. Elgamel, Magdy A. Bayoumi, Ahmed M. Shams, Bertrand Y. Zavidovique

J. Circuits Syst. Comput., 2004

2002

Performance analysis of low-power 1-bit CMOS full adder cells.

Ahmed M. Shams, Tarek Darwish, Magdy A. Bayoumi

IEEE Trans. Very Large Scale Integr. Syst., 2002

A Low Power High Performance Distributed DCT Architecture.

Ahmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

2001

Enhanced low power motion estimation VLSI architectures for video compression.

Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Hybrid Mesh-Based/Block-Based Motion Compensation Architecture.

Ahmed M. Shams, Mohamed A. Elgamel, Magdy A. Bayoumi

Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001

2000

A high-performance 1D-DCT architecture.

Ahmed M. Shams, Wendi Pan, Archana Chandanandan, Magdy A. Bayoumi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 108 Gbps, 1.5 GHz 1D-DCT Architecture.

Ahmed M. Shams, Magdy A. Bayoumi

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Performance evaluation of 1-bit CMOS adder cells.

Ahmed M. Shams, Magdy A. Bayoumi

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A New Full Adder Cell for Low-Power Applications.

Ahmed M. Shams, Magdy A. Bayoumi

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998