Ahmed Louri
Orcid: 0000-0003-4262-6688
According to our database1,
Ahmed Louri
authored at least 127 papers
between 1987 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For contributions to optical interconnection networks for parallel computing".
Timeline
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On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration.
IEEE Trans. Parallel Distributed Syst., February, 2024
A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration.
IEEE Trans. Parallel Distributed Syst., January, 2024
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.
IEEE Trans. Sustain. Comput., 2024
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.
J. Comput. Sci. Technol., February, 2023
IEEE Trans. Sustain. Comput., 2023
A Technique for Approximate Communication in Network-on-Chips for Image Classification.
IEEE Trans. Emerg. Top. Comput., 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design.
IEEE Trans. Sustain. Comput., 2022
IEEE Trans. Sustain. Comput., 2022
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing.
IEEE Trans. Parallel Distributed Syst., 2022
SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures.
IEEE Trans. Sustain. Comput., 2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning.
IEEE Trans. Parallel Distributed Syst., 2020
IEEE Trans. Parallel Distributed Syst., 2020
Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture.
IEEE Micro, 2020
DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies.
IEEE Trans. Sustain. Comput., 2019
Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques.
IEEE Trans. Computers, 2019
Utility-based resource management in an oversubscribed energy-constrained heterogeneous environment executing parallel applications.
Parallel Comput., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
An online quality management framework for approximate communication in network-on-chips.
Proceedings of the ACM International Conference on Supercomputing, 2019
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs.
IEEE Comput. Archit. Lett., 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
Design of high bandwidth photonic NoC architectures using optical multilevel signaling.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing.
Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures.
IEEE Trans. Computers, 2015
IEEE Comput. Archit. Lett., 2015
Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015
2014
Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration.
IEEE Trans. Computers, 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC).
J. Parallel Distributed Comput., 2011
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
A multilayer nanophotonic interconnection network for on-chip many-core communications.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.
IEEE Trans. Computers, 2008
IEEE Micro, 2008
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007
Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007
2006
A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems.
Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006
2005
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors.
IEEE Micro, 2005
2004
An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs).
IEEE Trans. Parallel Distributed Syst., 2004
A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
2000
A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems.
IEEE Trans. Parallel Distributed Syst., 2000
The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module.
Proceedings of the 29th Applied Image Pattern Recognition Workshop (AIPR 2000), 2000
1999
A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System.
Proceedings of the Parallel and Distributed Processing, 1999
1998
A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing.
IEEE Trans. Parallel Distributed Syst., 1998
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998
1995
IEEE Micro, 1995
1994
Computer, 1994
Computer, 1994
1993
J. Parallel Distributed Comput., 1993
Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992
A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
1991
Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing.
IEEE Micro, 1991
Proceedings of the PARLE '91: Parallel Architectures and Languages Europe, 1991
Design of an Optical Content-Addressable Parallel Processor with Applications to Fast Searching and Information Retrieval.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems.
Proceedings of the International Conference on Parallel Processing, 1991
1990
A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing.
Proceedings of the ACM 18th Annual Computer Science Conference on Cooperation, 1990
1988
A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988
Optical Arithmetic Using Signed-Digit Symbolic Substitution.
Proceedings of the International Conference on Parallel Processing, 1988
1987
A Parallel Architecture for Optical Computing.
Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing, 1987